PRELIMINARY

10

PRELIMINARY

Rev F

CPC5750

2. Control Registers

The control registers are used to set up operating characteristics, transmit/receive gains, PCM time slot assignments

and GPIO control. Access to these registers is dependent on the transmission mode set by the logical state of SDI

(pin 10) during a Reset or Power-Up event. With SDI held at a logic high, the device is configured for PCM Mode and

register access is only available via the SPI bus. When SDI is held at a logic low, the device is configured for IOM-2

GCI Mode and register access is only available through the GCI data link.

NOTE: PCLK and FS must be active before a write command is issued to the control registers, otherwise the written

values will not be retained.

Power Up and Reset events set the device’s Power Down bit (PD) to a logic high which disables the input and output

a high impedance state. After provisioning the control registers and if necessary, assigning the PCM interface to the

proper time slot, PD can be set low to begin operation. The GCI Mode does not allow changing the time slot of the

digitized voice data.

The table below shows the CPC5750 control register names, the bit names, and the register address. Access to the

registers is only available via read or write commands. The structure of a register command consists of two parts; first

is the command type nibble which is followed immediately by the register address nibble. Write commands will be

followed by the data word to be stored in the addressed register. The first four bits (nibble) of a read command are

1010 (0xA) while the write command’s first four bits (nibble) are 1011 (0xB). Following the command type nibble is the

register address nibble as provided in the table below. As an example, the command to read back the value

provisioned into the PCM Transmit Time Slot register is: 0xA7. Detailed discussions of each register are provided in

the following sections.

Table 1: Control Registers

NOTE: All registers are Read / Write and all user defined bits are Read / Write.

Register Name

(MSB)

Bits

(LSB)

Address

7

6

5

4

3

2

1

0

Dec

Hex

Mode Control

Companding

Not Used

ALB

DLB

PD

CPB

TXZ

TM

0

0x0

TX Gain: ±1dB Steps

Not Used

[4:0]

1

0x1

TX Gain: ±0.1dB Steps

Not Used

[3:0]

2

0x2

RX Gain: ±1dB Steps

Not Used

[4:0]

3

0x3

RX Gain: ±0.1dB Steps

Not Used

[3:0]

4

0x4

Not Used

[6:0]

50x5

Not Used

[2:0]

6

0x6

Not Used

[6:0]

70x7

Not Used

[2:0]

8

0x8

Reserved

00000000

9

0x9

GPIO Control

DIR(3)

DIR(2)

DIR(1)

DIR(0)

D(3)

D(2)

D(1)

D(0)

10

0xA