PRELIMINARY

Rev F

PRELIMINARY

23

CPC5750

6. IOM-2 (GCI) Interface

IOM-2 is a superset specification that includes the General Circuit Interface (GCI), the line card portion of the

specification. The CPC5750 implements the GCI part of this bus as specified in the Advanced Micro Devices

document, IOM-2 Interface Reference Guide.

The GCI bus has an 8kHz frame sync pulse that indicates the start of each frame. Each frame consists of 8 sub-frame

locations with 4 bytes per sub-frame. The CPC5750 can be configured to transmit and receive on any of these

sub-frames. The selection of which sub-frame to use is done with the three pins; SCLK, SDO and SFSEL. The SPI

pins SCLK and SDO are utilized since the SPI bus is not used when in the GCI Mode. The logical value of these three

inputs when reset is complete sets the sub-frame assignment. Sub-Frame assignments are shown in logic table

below.

Table 4:

GCI Mode Sub-Frame Selection

The 4 bytes within each sub-frame are considered communication channels. The 32 bits of the sub-frame are

designated for specific use by the standard. Each sub-frame can support a pair of codecs, one each for channels B1

& B2. Although the CPC5750 uses the entire sub-frame, only B1 is used.

(32 bits per sub-frame) x (8 sub-frames) x (8kHz frame rate) x (2 clocks per bit) = 4.096MHz clock. There is also a

mode that uses 1 clock per bit for a 2.048MHz clock rate.

Figure 7: GCI Sub-Frame Makeup

B1:

Channel slot used to transmit and receive audio data by CPC5750

M:

Channel used to read and write CPC5750 control registers

SC:

Channel used to control CPC5750 register access

SCLK

SDO

SFSEL

Sub-Frame

LL

L0

LL

H1

LH

L2

LH

H3

HL

L4

HL

H5

HH

L6

HH

H7

FSYNC

125

µs

SF0

SF1

SF2

SF3

SF4

SF5

SF6

SF7

Sub-Frame

61

1

8

0

B1

8

1

B2

8

2

M

C/I

MR MX

Channel

SC Channel

Time-Multiplexed GCI Frame Structure