PRELIMINARY

Rev F

PRELIMINARY

19

CPC5750

correct data before the FS signal is detected. For this to happen, the CPC5750 must count the PCLK cycles in the first

the FS pulse does not arrive as predicted, then the CPC5750 will re-synchronize, and recount the time slots in the

frame. For this reason the data in the first two received frames after connection to a PCM bus will be ignored and no

data will be transmitted upstream.

Detection of the FS pulse with the PCLK falling edge eliminates the rigid FS pulse width constraints and the required

synchronization of the FS rising edge with the PCLK rising edge. The minimum FS pulse width is the sum of the setup

and hold times while the maximum pulse width must allow for a minimum of one FS low detect by the falling PCLK

edge.

Assuring the first upstream data bit is available with the rising edge of FS and allowing the FS pulse to persist for

multiple PCLK cycles provides compatibility with the legacy Long Frame Sync, Non-delayed Timing Mode when the

time slot and bit delay setting registers are configured for the first bit of the first time slot, (Time Slot 0 {zero} and no bit

delay) of the frame. Additionally, since the CPC5750 is designed to accept small FS pulses and can be provisioned for

the transfer of data delayed by one or more bits it is compatible with the legacy Short Frame Sync Delayed Timing

Mode. As with the legacy data bit stream formats, the Most Significant Bit (MSB) will be the first bit received and the

first bit transmitted in the data byte.

Figure 1: PCM Time Slot 0, Short FS, No Bit Delay (PTC=PRC=0, PTB=PRB=0, CPB=0, TXZ=1)

LSB

LSB

MSB

MSB

HI-Z

HI-Z

PCLK

FS

FRAME BIT

D

RX

D

TX

1

18

234567

8

9

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