ADF4155

Data Sheet

REGISTER 5

Register 5 Control Bits

With Bits[C4:C1] set to 0101, Register 5 is programmed. Figure 29

shows the input data format for programming this register.

Pulse Bleed Delay

In some cases, pulsed bleed (DB25) can improve spurious

performance compared to constant negative bleed. If enabling

pulsed bleed, disable the constant negative bleed bit (Register 6,

Bit DB12). Pulsed bleed works by adding a programmable delay

to the charge pump down pulse, thereby introducing a phase

offset in the loop and improving the linearity of the charge

pump. The advantage over the constant negative bleed is that

the programmable delay is only on for a short time within one

PFD period compared to the constant negative bleed which is

constantly on. This pulsed bleed can improve the spurious

performance. The downside of a pulsed bleed is that there is less

resolution to program the amount of bleed compared to the

constant negative bleed.

The pulsed bleed delay is programmed using Bits[DB27:DB26].

Selecting the pulsed bleed delay so that the phase offset is

<90 degrees is recommended.

Pulse bleed on the ADF4155 can be activated by setting

Bit DB25 to 1 (see Figure 29).

Antibacklash Pulse (ABP) Select

Set DB23 to 0 to select the pulsed bleed delay, Bits[DB27:DB26]

as the antibacklash pulse width. The recommended default

setting is pulse bleed delay (2.6 ns). The pulse bleed delay bits

(DB27:DB26) function as the antibacklash pulse width

irrespective of whether the pulse bleed is enabled or disabled.

Set DB23 to 1 to use a narrow antibacklash pulse width of

1.6 ns. For PFD frequencies greater than 80 MHz, it is

recommended to use the 1.6 ns pulse width.

Cycle Slip Reduction (CSR)

Setting DB19 to 1 enables cycle slip reduction. When using

cycle slip reduction, the signal at the PFD must have a 50% duty

cycle for the cycle slip reduction to work. The charge pump

current setting must also be set to a minimum. Refer to the

Cycle Slip Reduction for Faster Lock Times section for more

information.

Figure 29. Register 5 (R5)

CSR

CYCLE SLI P

REDUCTION

0

DISABLED

1

ENABLED

PB

PULSE BLEED

0

DISABLED

1

ENABLED

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

PB2

PB1

0

PB

0

RESERVED

CONTROL BITS

ABP

0

0

0

CSR

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

C3(1) C2(0) C1(1)

C4(0)

0

0

0

RESERVED

RESERVED

ABP

ANTIBACKLASH PULSE

WIDTH SELECT

0

PULSE BLEED DEL AY

1

1.6ns

PB1

PULSE BLEED

DELAY

PB2

0

0

1

1

0

1

0

1

2.6ns

3.6ns

4.8ns

6.0ns

Rev. 0 | Page 22 of 32