LTC6948 datasheet(20/38 Pages) AD

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LTC6948

6948fa

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operaTion

LDO REGULATOR

Theadjustablelowdropout(LDO)regulatorsuppliespower

to the Δ∑ modulator. The regulator requires a low ESR

ceramic capacitor (ESR < 0.8Ω) connected to the LDO

pin (pin 7) for stability. The capacitor value may range

from 0.047µF to 1µF.

TheLDOvoltageissetusingtheLDOV[1:0]bits,andshould

be chosen based upon the fPFD frequency to minimize

power and spurious. The regulator is disabled by setting

the LDOEN bit to 0. When disabled by using either the

LDOEN or PDFN bits, the LDO pin is connected directly

to VD+ using a low impedance switch, and the regulator

is powered down. See Table 13 for programming details.

Table 13. LDOV[1:0] and LDOEN Programming

LDOV[1:0]

LDOEN

VLDO

fPFD

1.7V

≤34.3MHz

2.0V

≤45.9MHz

2.3V

≤56.1MHz

2.6V

≤66.3MHz

VD+

≤76.1MHz

OUTPUT (O) DIVIDER

The 3-bit O divider can reduce the frequency from the VCO

to extend the output frequency range. Its divide ratio O

may be set to any integer from 1 to 6, inclusive, outputting

a 50% duty cycle even with odd divide values. Use the

OD[2:0] bits found in register h0B to directly program the

O divide ratio. See the Applications Information section

for the relationship between O and the fREF, fPFD, fVCO,

and fRF frequencies.

RF OUTPUT BUFFER

The low noise, differential output buffer produces a dif-

ferential output power of –4.3dBm to +4.5dBm, settable

with bits RFO[1:0] according to Table 14. The outputs may

becombinedexternally,orusedindividually.Terminateany

unused output with a 50Ω resistor to VRF+.

Table 14. RFO[1:0] Programming

RFO[1:0}

PRF (DIFFERENTIAL)

PRF (SINGLE-ENDED)

–4.3dBm

–7.3dBm

–1.5dBm

–4.5dBm

1.6dBm

–1.4dBm

4.5dBm

1.5dBm

Each output is open-collector with 136Ω pull-up resistors

to VRF+, easing impedance matching at high frequencies.

See Figure 5 for circuit details and the Applications Infor-

mation section for matching guidelines. The buffer may be

muted with either the OMUTE bit, found in register h02,

or by forcing the MUTE input low.

6948 F05

VRF+

RF+

136

RF–

MUTE

OMUTE

RFO[1:0]

MUTE

Figure 5. Simplified RF Interface Schematic

SERIAL PORT

The SPI-compatible serial port provides control and

monitoring functionality. A configurable status output

STAT gives additional instant monitoring.

Communication Sequence

The serial bus is comprised of CS, SCLK, SDI, and SDO.

Data transfers to the part are accomplished by the se-

rial bus master device first taking CS low to enable the

LTC6948’s port. Input data applied on SDI is clocked on

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