ZXLD1371Q

ZXLD1371Q

Document number: DS37116 Rev. 1 - 2

6 of 42

www.diodes.com

September 2015

© Diodes Incorporated

ZXLD1371Q

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Output Parameters

FLAG pin low level output voltage

Output sinking 1mA

—

—

0.5

V

FLAG pin open-drain leakage current

—

—

1

µA

STATUS Flag no-load output voltage

(Note 13)

Normal operation

4.2

4.5

4.8

V

(Note 14)

3.3

3.6

3.9

3.3

3.6

3.9

3.3

3.6

3.9

1.5

1.8

2.1

Excess sense resistor current

0.6

0.9

1.2

Output impedance of STATUS output

Normal operation

—

10

—

kΩ

Driver output (PIN GATE)

High level output voltage

No load Sourcing 1mA

(Note 15)

10

11

—

V

Low level output voltage

Sinking 1mA, (Note 16)

—

—

0.5

V

High level GATE CLAMP voltage

—

12.8

15

V

Dynamic peak current available during rise

or fall of output voltage

Charging or discharging gate of external

—

±300

—

mA

Time to assert ‘STALL’ flag and

warning on STATUS output

(Note 17)

GATE low or high

—

100

170

µs

Upper threshold voltage

falling)

560

625

690

mV

Lower threshold voltage

Output current reduced to <10% of set

380

440

500

mV

—

—

1

µA

Notes:

13. In the event of more than one fault/warning condition occurring, the higher priority condition will take precedence.

For example

‘Excessive coil current’ and ‘Out of regulation’ occurring together will produce an output of 0.9V on the STATUS pin.

an overcurrent status may be indicated when operating at high boost ratios

– this due to the feedback loop increasing the sense voltage.

For more information see the Application Information section about Flag/Status levels.

exceeding 15V.

16. GATE is switched to PGND by an NMOS transistor.

grounded internally and the SHP pin is switched to its nominal operating voltage, before operation is allowed to resume. Restart cycles will be

off until normal operation is possible.