¡ Semiconductor

MSM548331

9/23

access can be achieved independently from read initial address reset cycles.

Input addresses are stored into address registers which are connected with address counter which

controls address pointer operation. In the serial access operation, the input address into the address

registers are kept.

starting serial read or write just after the initial read or write address reset cycles.

Refer to the "FUNCTION TABLE" shown later.

1. Line hold operation (read only)

By the "Line hold operation" logic which is composed by a combination of control inputs' level,

access is executed starting from the first word on the current line.

2. Original address reset operation

By the "Original address reset" logic, the address counter is reset to (0,0). After the reset mode,

serial access starts from the address (0,0) .

The address counter is reset by this reset mode but the address register, which stored input

addressinthepreviousaddressresetcycleoraddresssetcycle,isnotreset.Thenon-initialized

address can be used as a preset address in "address jump reset" mode.

3. Line increment operation

By the "Line increment operation" logic, the X address counter is incremented by one from the

current X address. That is, serial access from the Y = (0) on the next line is enabled.

4. Address jump operation

By the "Address jump operation" logic, a jump may be caused to the initialized line address.

Note : During one reset setting cycle, a plurality of resets cannot be set.

Power ON

Power must be applied to RCLK, RE, OE, WCLK, WE and IE input signals to pull them "Low" before

reached the specified voltage. After 200 ms, a minimum of one line dummy write operation and read

operation is required according to the address setting mode, because the read and write address

pointers are not valid after power-up.

New Data Read Access

In order to read out "new data', the delay between the beginning of a write address setting cycle and

read address setting cycle must be at least two lines.

Old Data Read Access

In order to read out "old data", the delay between the beginning of a write address setting cycle and

read address setting cycle must be more than 0 but less than a half line.