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Bosch Sensortec | BMP388 Datasheet

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Modifications reserved |Data subject not change without notice | Printed in Germany

Document number: BST-BMEP388-DS001-01 Revision_1.1_032018

tHDDAT

tBUF

SDI

SCK

SDI

tLOW

tHDSTA

tSUSTA

tHIGH

tSUDAT

tSUSTO

Figure 21: I²C timing diagram

Table 47: I²C timings

Parameter

Symbol

Condition

Min

Typ

Max

Units

SCK frequency

Fi2c

400

3400

kHz

SDI input setup time

tSU;DAT

S&F Mode

HS mode

160

SDI output hold time

tHD;DAT

S&F Mode, Cb≤100 pF

S&F Mode, Cb≤400 pF

HS mode, Cb≤100 pF

HS mode, Cb≤400 pF

SCK low pulse

tLOW

HS mode, Cb≤100 pF

VDDIO = 1.62 V

160

SCK low pulse

tLOW

HS mode, Cb≤100 pF

VDDIO = 1.2 V

210

The above-mentioned I2C specific timings correspond to the following internal added delays:



Input delay between SDI and SCK inputs: SDI is more delayed than SCK by typically 120 ns in Standard and Fast

Modes and by typically 20 ns in High Speed Mode.



Output delay from SCK falling edge to SDI output propagation is typically 140 ns in Standard and Fast Modes and

typically 70 ns in High Speed Mode.

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