28 / 64 page
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 28 of 64
Typical 3.3V Power Consumption
CY37032V
CY37064V
0
5
10
15
20
25
30
0
2 0
4 0
6 0
80
1 00
120
140
160
Freq uenc y (M H z)
L o w Po we r
High S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
5
10
15
20
25
30
35
40
45
0
2 0
4 0
6 0
8 0
100
120
140
Fre q u e nc y (M H z )
Low P o w e r
Hig h S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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