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Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 30 of 64
CY37256V
CY37384V
Typical 3.3V Power Consumption (continued)
0
20
40
60
80
100
120
140
0
2 0
4 0
6 0
8 0
1 00
120
F r e quency ( M H z )
Lo w P o w e r
Hig h S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
20
40
60
80
100
120
140
160
180
200
0
1 0
2 0
3 04 05 0
6 07 08 0
9 0
Fr e quenc y ( M H z )
Lo w P o w e r
H igh S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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