NT5CB128M8GP-EKB datasheet(61/160 Pages) NANYA

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Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

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DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Refresh Command

The Refresh command (REF) is used during normal operation of the DDR3(L) SDRAMs. This command is not persistent,

so it must be issued each time a refresh is required. The DDR3(L) SDRAM requires Refresh cycles at an average periodic

interval of tREFI. When

, RA, and A are held Low and WE High at the rising edge of the clock, the chip enters a

Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before

the Refresh Command can be applied. The refresh addressing is generated by the internal refresh controller. This makes

the address bits “Don’t Care” during a Refresh command. An internal address counter suppliers the address during the

refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has

completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Refresh Command and the

next valid command, except NOP or DES, must be greater than or equal to the minimum Refresh cycle time tRFC(min) as

shown in the following figure.

In general, a Refresh command needs to be issued to the DDR3(L) SDRAM regularly every tREFI interval. To allow for

improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided.

A maximum of 8 Refresh commands can be postponed during operation of the DDR3(L) SDRAM, meaning that at no point

in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8 Refresh commands are

postponed in a row, the resulting maximum interval between the surrounding Refresh commands is limited to 9 x tREFI. A

maximum of 8 additional Refresh commands can be issued in advance (“pulled in”), with each one reducing the number of

regular Refresh commands required later by one. Note that pulling in more than 8 Refresh commands in advance does not

further reduce the number of regular Refresh commands required later, so that the resulting maximum interval between two

surrounding Refresh command is limited to 9 x tREFI. Before entering Self-Refresh Mode, all postponed Refresh

commands must be executed.

Self-Refresh Entry/Exit Timing

Postponing Refresh Commands (Example)

Ta0

Tb0

Tb1

Tb3

Ta1

Tb2

NOP

CMD

NOP

REF

Valid

NOP

REF

NOP

Valid

REF

Tc0

Tc1

Valid

tRFC

tRFC(min)

tREFI (max, 9 x tREFI)

DRAM must be idle

Time Break

9 x tREFI

tREFI

tRFC

8 REF-Command postponed

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