NT5CB128M8GP-EKB datasheet(84/160 Pages) NANYA

84 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

ZQ Calibration Commands

ZQ Calibration Description

ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3(L) SDRAM needs longer time to calibrate

output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic calibrations.

ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be

issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine

inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM IO

which gets reflected as updated output driver and on-die termination values.

The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the

transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing

period of tZQoper.

ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing

window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS

command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and RTT impedance error within 64 nCK for

all speed bins assuming the maximum sensitivities

specified in the ‘Output Driver Voltage and Temperature Sensitivity’ and

‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined

from these tables and other application-specific parameters. One method for calculating the interval between ZQCS

commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the

application, is illustrated. The interval could be defined by the following formula:

where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and

voltage sensitivities.

For example, if TSens = 1.5% / oC, VSens = 0.15% / mV, Tdriftrate = 1 oC / sec and Vdriftrate = 15 mV / sec, then the

interval between ZQCS commands is calculated as:

No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper, or

tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values. Once DRAM

calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.

All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.

ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-refresh

exit, DDR3(L) SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The earliest possible

time for ZQ Calibration command (short or long) after self refresh exit is tXS.

In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit, or

tZQCS between ranks.

NT5CB128M8GP-EKB Datasheet(PDF) 84 Page - Nanya Technology Corporation.