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NT5CB128M8GP-EKB Datasheet(PDF) 26 Page - Nanya Technology Corporation. |
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NT5CB128M8GP-EKB Datasheet(HTML) 26 Page - Nanya Technology Corporation. |
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26 / 160 page  Version 2.2 26 Nanya Technology Cooperation © 04/2019 All Rights Reserved. NTC Proprietary Level: Property DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP Mode Register MR3 The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on , RA, A, WE high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to the table below. MR3 Definition BA2 BA1 BA0 A15-A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓ 0 MPR A2 A1 A0 0 0 0 1 0 1 1 0 BA1 BA0 MR select 1 1 0 0 MR0 0 1 MR1 1 0 MR2 1 1 MR3 Normal operation Dataflow from MPR MPR Loc 0 Predefined pattern Reserved Reserved Reserved MPR Loc MPR MR select * 1 : BA2, A3 - A15 are RFU and must be programmed to 0 during MRS. * 2 : The predefined pattern will be used for read synchronization. * 3 : When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored. |
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