NT5CB128M8GP-EKB datasheet(121/160 Pages) NANYA

121 / 160 page

Version 2.2

121

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Input/Output Capacitance

Parameter

Symbol

800

1066

1333

1600

1866

2133

Unit

Notes

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Input/output capacitance

(DQ, DM, DQS,

,

TDQS,

T)

CIO

(DDR3)

1.4

3.0

1.4

2.7

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1,2,3

CIO

(DDR3L)

1.4

2.5

1.4

2.5

1.4

2.3

1.4

2.2

1.4

2.1

1,2,3

Input capacitance, CK and



CCK

0.8

1.6

0.8

1.6

0.8

1.4

0.8

1.4

0.8

1.3

0.8

1.3

2,3

Input capacitance delta, CK and



CDCK

0.15

2,3,4

Input/output capacitance delta

DQS and



CDDQS

0.15

2,3,5

Input capacitance,

(CTRL, ADD,CMD input-only pins)

(DDR3)

0.75

1.4

0.75

1.35

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

2,3,6

(DDR3L)

0.75

1.3

0.75

1.3

0.75

1.3

0.75

1.2

0.75

1.2

2,3,6

Input capacitance delta,

(All CTRL input-only pins

CDI_CTRL

-0.5

0.3

-0.5

0.3

-0.4

0.2

-0.4

0.2

-0.4

0.2

-0.4

0.2

2,3,7,8

Input capacitance delta,

(All ADD/CMD input-only pins)

CDI_ADD_

CMD

-0.5

0.5

-0.5

0.5

-0.4

0.4

-0.4

0.4

-0.4

0.4

-0.4

0.4

2,3,9,

Input/output capacitance delta, DQ,

DM, DQS,

, TDQS, T

CDIO

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

-0.5

0.3

2,3,11

Input/output capacitance of ZQ pin

CZQ

2,3,12

NOTE 1. Although the DM, TDQS and

T pins have different functions, the loading matches DQ and DQS

NOTE 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured

according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER(VNA)”)

with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE,

REET and ODT as necessary).

VDD=VDDQ=1.5V, VBIAS=VDD/2 and ondie termination off.

NOTE 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here

NOTE 4. Absolute value of CCK-



NOTE 5. Absolute value of CIO(DQS)-CIO(

)

NOTE 6. CI applies to ODT,

, CKE, A0-A13, BA0-BA2, RA, A, WE.

NOTE 7. CDI_CTRL applies to ODT,

 and CKE

NOTE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(

L))

NOTE 9. CDI_ADD_CMD applies to A0-A13, BA0-BA2,

RA, A and WE

NOTE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(

L))

NOTE 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(

))

NOTE 12. Maximum external load capacitance on ZQ pin: 5 pF.

NT5CB128M8GP-EKB Datasheet(PDF) 121 Page - Nanya Technology Corporation.

NT5CB128M8GP-EKB Datasheet(HTML) 121 Page - Nanya Technology Corporation.

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