PIC18F44800TESLASHML datasheet(478/484 Pages) MICROCHIP

478 / 484 page

PIC18F2480/2580/4480/4580

DS39637A-page 476

Preliminary

 2004 Microchip Technology Inc.

Special Function Registers ................................................ 71

Map ...................................................................... 71–76

SPI Mode (MSSP)

Associated Registers ............................................... 195

Bus Mode Compatibility ........................................... 195

Effects of a Reset ..................................................... 195

Enabling SPI I/O ...................................................... 191

Master Mode ............................................................ 192

Master/Slave Connection ......................................... 191

Operation ................................................................. 190

Operation in Power Managed Modes ...................... 195

Serial Clock .............................................................. 187

Serial Data In ........................................................... 187

Serial Data Out ........................................................ 187

Slave Mode .............................................................. 193

Slave Select ............................................................. 187

Slave Select Synchronization .................................. 193

SPI Clock ................................................................. 192

Typical Connection .................................................. 191

SS .................................................................................... 187

SSPOV ............................................................................. 217

SSPOV Status Flag .......................................................... 217

SSPSTAT Register

R/W Bit ............................................................. 200, 201

Stack Full/Underflow Resets .............................................. 64

Status Register ................................................................... 88

SUBFSR ........................................................................... 407

SUBFWB .......................................................................... 396

SUBLW ............................................................................ 397

SUBULNK ........................................................................ 407

SUBWF ............................................................................ 397

SUBWFB .......................................................................... 398

SWAPF ............................................................................ 398

Table Pointer Operations (table) ........................................ 98

Table Reads/Table Writes .................................................. 64

TBLRD ............................................................................. 399

TBLWT ............................................................................. 400

Time-out in Various Situations (table) ................................ 45

Timer0 .............................................................................. 147

16-Bit Mode Reads and Writes ................................ 148

Associated Registers ............................................... 149

Clock Source Edge Select (T0SE Bit) ...................... 148

Clock Source Select (T0CS Bit) ............................... 148

Operation ................................................................. 148

Overflow Interrupt .................................................... 149

Prescaler. See Prescaler, Timer0.

Timer1 .............................................................................. 151

16-Bit Read/Write Mode ........................................... 153

Associated Registers ............................................... 155

Interrupt .................................................................... 154

Operation ................................................................. 152

Oscillator .......................................................... 151, 153

Oscillator Layout Considerations ............................. 154

Overflow Interrupt .................................................... 151

Resetting, Using a Special Event

Trigger Output (CCP) ....................................... 154

Special Event Trigger (ECCP) ................................. 174

TMR1H Register ...................................................... 151

TMR1L Register ....................................................... 151

Use as a Real-Time Clock ....................................... 154

Timer2 .............................................................................. 157

Associated Registers ............................................... 158

Interrupt ................................................................... 158

Operation ................................................................. 157

Output ...................................................................... 158

PR2 Register ................................................... 169, 175

TMR2 to PR2 Match Interrupt .......................... 169, 175

Timer3 .............................................................................. 159

16-Bit Read/Write Mode .......................................... 161

Associated Registers ............................................... 161

Operation ................................................................. 160

Oscillator .......................................................... 159, 161

Overflow Interrupt ............................................ 159, 161

Special Event Trigger (CCP) ................................... 161

TMR3H Register ...................................................... 159

TMR3L Register ....................................................... 159

Timing Diagrams

A/D Conversion ........................................................ 451

Acknowledge Sequence .......................................... 220

Asynchronous Reception ......................................... 239

Asynchronous Transmission .................................... 237

Asynchronous Transmission (Back to Back) ........... 237

Automatic Baud Rate Calculation ............................ 235

Auto-Wake-up Bit (WUE) During

Normal Operation ............................................ 240

Auto-Wake-up Bit (WUE) During Sleep ................... 240

Baud Rate Generator with Clock Arbitration ............ 214

BRG Overflow Sequence ......................................... 235

BRG Reset Due to SDA Arbitration

During Start Condition ..................................... 223

Brown-out Reset (BOR) ........................................... 437

Bus Collision During a Repeated

Start Condition (Case 1) .................................. 224

Bus Collision During a Repeated

Start Condition (Case 2) .................................. 224

Bus Collision During a Start Condition

(SCL = 0) ......................................................... 223

Bus Collision During a Start Condition

(SDA only) ....................................................... 222

Bus Collision During a Stop Condition

(Case 1) ........................................................... 225

Bus Collision During a Stop Condition

(Case 2) ........................................................... 225

Bus Collision for Transmit and Acknowledge .......... 221

Capture/Compare/PWM (CCP) ............................... 439

CLKO and I/O .......................................................... 436

Clock Synchronization ............................................. 207

EUSART Synchronous Receive

(Master/Slave) ................................................. 449

EUSART Synchronous Transmission

(Master/Slave) ................................................. 449

Example SPI Master Mode (CKE = 0) ..................... 441

Example SPI Master Mode (CKE = 1) ..................... 442

Example SPI Slave Mode (CKE = 0) ....................... 443

Example SPI Slave Mode (CKE = 1) ....................... 444

External Clock (All Modes except PLL) ................... 434

Fail-Safe Clock Monitor ........................................... 356

First Start Bit Timing ................................................ 215

Full-Bridge PWM Output .......................................... 179

Half-Bridge PWM Output ......................................... 178

High/Low-Voltage Detect (VDIRMAG = 0) ............... 269

High/Low-Voltage Detect (VDIRMAG = 1) ............... 270

PIC18F44800TE/ML Datasheet(PDF) 478 Page - Microchip Technology

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