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PIC18F44800TE/ML Datasheet(PDF) 479 Page - Microchip Technology |
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PIC18F44800TE/ML Datasheet(HTML) 479 Page - Microchip Technology |
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479 / 484 page  2004 Microchip Technology Inc. Preliminary DS39637A-page 477 PIC18F2480/2580/4480/4580 I2C Bus Data ............................................................ 445 I2C Bus Start/Stop Bits ............................................. 445 I2C Master Mode (7 or 10-Bit Transmission) ........... 218 I2C Master Mode (7-Bit Reception) .......................... 219 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 204 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 209 I2C Slave Mode (10-Bit Transmission) ..................... 205 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 202 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 208 I2C Slave Mode (7-Bit Transmission) ....................... 203 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 210 Master SSP I2C Bus Data ........................................ 447 Master SSP I2C Bus Start/Stop Bits ........................ 447 Parallel Slave Port (PIC18F4480/4580) ................... 440 Parallel Slave Port (PSP) Read ............................... 145 Parallel Slave Port (PSP) Write ............................... 145 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 184 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 184 PWM Direction Change ........................................... 181 PWM Direction Change at Near 100% Duty Cycle ............................................. 181 PWM Output ............................................................ 169 Repeat Start Condition ............................................. 216 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ................................. 437 Send Break Character Sequence ............................ 241 Slave Synchronization ............................................. 193 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 47 SPI Mode (Master Mode) ......................................... 192 SPI Mode (Slave Mode with CKE = 0) ..................... 194 SPI Mode (Slave Mode with CKE = 1) ..................... 194 Stop Condition Receive or Transmit Mode .............. 220 Synchronous Reception (Master Mode, SREN) ..................................... 244 Synchronous Transmission ...................................... 242 Synchronous Transmission (Through TXEN) .......... 243 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) ............................. 47 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ....................... 46 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ....................... 46 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise TPWRT) .............. 46 Timer0 and Timer1 External Clock .......................... 438 Transition for Entry to Idle Mode ................................ 38 Transition for Entry to SEC_RUN Mode .................... 35 Transition for Entry to Sleep Mode ............................ 37 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 354 Transition for Wake from Idle to Run Mode ............... 38 Transition for Wake from Sleep (HSPLL) ................... 37 Transition from RC_RUN Mode to PRI_RUN Mode ................................................. 36 Transition from SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 35 Transition to RC_RUN Mode ..................................... 36 Timing Diagrams and Specifications ............................... 434 A/D Conversion Requirements ................................ 451 AC Characteristics Internal RC Accuracy ....................................... 435 Capture/Compare/PWM Requirements ................... 439 CLKO and I/O Requirements ................................... 436 EUSART Synchronous Receive Requirements .................................................. 449 EUSART Synchronous Transmission Requirements .................................................. 449 Example SPI Mode Requirements Master Mode, CKE = 0 .................................... 441 Master Mode, CKE = 1 .................................... 442 Slave Mode, CKE = 0 ...................................... 443 Slave Mode, CKE = 1 ...................................... 444 External Clock Requirements .................................. 434 High/Low-Voltage Detect Characteristics ................ 431 I2C Bus Data Requirements (Slave Mode) .............. 446 Master SSP I2C Bus Data Requirements ................ 448 Master SSP I2C Bus Start/Stop Bits Requirements ........................................... 447 Parallel Slave Port Requirements (PIC18F4480/4580) ......................................... 440 PLL Clock ................................................................ 435 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ............... 437 Timer0 and Timer1 External Clock Requirements ........................................ 438 Top-of-Stack Access .......................................................... 62 TRISE Register PSPMODE Bit ......................................................... 138 TSTFSZ ........................................................................... 401 Two-Speed Start-up ................................................. 343, 354 Two-Word Instructions Example Cases ......................................................... 66 TXSTA Register BRGH Bit ................................................................. 231 V Voltage Reference Specifications .................................... 430 W Watchdog Timer (WDT) ........................................... 343, 352 Associated Registers ............................................... 353 Control Register ....................................................... 352 During Oscillator Failure .......................................... 355 Programming Considerations .................................. 352 WCOL ...................................................... 215, 216, 217, 220 WCOL Status Flag ................................... 215, 216, 217, 220 WWW, On-Line Support ...................................................... 5 X XORLW ........................................................................... 401 XORWF ........................................................................... 402 |
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