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SAFC161PI Datasheet(PDF) 127 Page - Infineon Technologies AG |
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SAFC161PI Datasheet(HTML) 127 Page - Infineon Technologies AG |
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127 / 400 page  &3, 3DUDOOHO 3RUWV User’s Manual 7-1 1999-08 7 Parallel Ports In order to accept or generate single external control signals or parallel data, the C161PI provides up to 76 parallel IO lines organized into six 8-bit IO ports (PORT0 made of P0H and P0L, PORT1 made of P1H and P1L, Port 2, Port 6), one 15-bit IO port (Port 3), one 7-bit IO port (Port 4) and one 6-bit input port (Port 5). These port lines may be used for general purpose Input/Output controlled via software or may be used implicitly by the C161PI’s integrated peripherals or the External Bus Controller. All port lines are bit addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers (except Port 5, of course). The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three IO ports (2, 3, 6) can be configured (pin by pin) for push/pull operation or open-drain operation via control registers. The logic level of a pin is clocked into the input latch once per state time, regardless whether the port is configured for input or output. Figure 7-1 SFRs and Pins associated with the Parallel Ports Data Input / Output Registers Direction Control Registers Diverse Control Registers ODP2 E ODP6 E P1L P1H DP1L E DP1H E P0L P0H DP0L E DP0H E ODP3 E P5DIDIS P3 P4 P5 P6 P2 DP3 DP4 DP6 DP2 PDCR E PICON E |
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