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SIP12201 Datasheet(PDF) 5 Page - Vishay Siliconix |
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SIP12201 Datasheet(HTML) 5 Page - Vishay Siliconix |
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5 / 11 page ![]() Document Number: 73541 S-52083–Rev. A, 10-Oct-05 www.vishay.com 5 Vishay Siliconix SiP12201 New Product Fault State: The IC can only enter into Fault mode after the soft start mode has ended and seven consecutive over cur- rent condition cycles has occurred. Once it enters the Fault state, with the High Side MOSFET turned off and the Low Side MOSFET turned on, any occurring over current condition will be ignored. The Fault State will last for seven soft start cycles. After which the IC will enter Soft Start mode. If the over current condition is removed the IC will operate normally, otherwise the over current sequence is repeated. This fault scheme minimizes thermal stress on the external power MOS- FET switches. Over Temperature: When the temperature of the chip goes above 165 °C, the chip enters into over temperature shutdown. The High Side gate will be off and the Low Side gate will be on. Only system monitor circuitry will be active. Once the temperature of the chip drops below 145 °C, the chip enters into the normal operation mode. Duty-Factor Limitations for Low VOUT / VIN Ratios The SiP12201 output voltage is adjustable down to 0.6 V. However, the minimum duty factor may limit the ability to supply low-voltage outputs from high voltage inputs. With high-input voltages, the required duty fac- tor is approximately: where RDS(ON) x ILOAD is the voltage drop across the synchronous rectifier. The SiP12201 minimum duty factor is 10%, so the maximum input voltage (VIN(MAX)) that can supply a given output voltage is: If the circuit cannot attain the required duty factor dic- tated by the input and output voltages, the output volt- age still remains in regulation. However, there may be intermittent or continuous half-frequency operations as the controller attempts to lower the average duty factor by deleting pulses. This can increase output voltage ripple and inductor current ripple, which increases noise and reduces efficiency. Furthermore, circuit sta- bility is not guaranteed. Setting the Output Voltage: An output voltage between 0.6 V and 5.5 V (if VIN is between 4.2 V and 6.0 V then the maximum VOUT is 0.9* VIN) and can be configured by connecting FB pin to a resistive divider between the output and GND. Select resistor R2 in the 1 k Ω to 10 kΩ range. R1 is then given by: where VFB = 0.6 V. () IN LOAD DS(ON) OUT V I R V × + ( ) LOAD DS(ON) OUT ) ( I R V 10 × + ≤ MAX IN V ( ) 1 V V R R FB OUT 2 1 − = R1 R2 0.6 V FB VOUT |
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