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PCF2127 Datasheet(PDF) 63 Page - NXP Semiconductors

Part # PCF2127
Description  Accurate RTC with integrated quartz crystal for industrial applications
PDF  100 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF2127 Datasheet(HTML) 63 Page - NXP Semiconductors

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PCF2127
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 8 — 19 December 2014
63 of 100
NXP Semiconductors
PCF2127
Accurate RTC with integrated quartz crystal for industrial applications
[1]
The chip enable must not be wired permanently LOW.
9.1.1 Data transmission
The chip enable signal is used to identify the transmitted data. Each data transfer is a
whole byte, with the Most Significant Bit (MSB) sent first.
The transmission is controlled by the active LOW chip enable signal SDA/CE. The first
byte transmitted is the command byte. Subsequent bytes are either data to be written or
data to be read (see Figure 37).
The command byte defines the address of the first register to be accessed and the
read/write mode. The address counter will auto increment after every access and will
reset to zero after the last valid register is accessed. The R/W bit defines if the following
bytes are read or write information.
Table 86.
Serial interface
Symbol
Function
Description
SDA/CE
chip enable input;
active LOW
[1] when HIGH, the interface is reset;
input may be higher than VDD
SCL
serial clock input
when SDA/CE is HIGH, input may float;
input may be higher than VDD
SDI
serial data input
when SDA/CE is HIGH, input may float;
input may be higher than VDD;
input data is sampled on the rising edge of
SCL
SDO
serial data output
push-pull output;
drives from VSS to Voper(int) (VBBS);
output data is changed on the falling edge of
SCL
Fig 37. Data transfer overview
Table 87.
Command byte definition
Bit
Symbol
Value
Description
7R/W
data read or write selection
0
write data
1
read data
6 to 5
SA
01
subaddress;
other codes will cause the device to ignore
data transfer
4 to 0
RA
00h to 1Dh
register address



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