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TMS320VC5507ZAY Datasheet(PDF) 63 Page - Texas Instruments |
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TMS320VC5507ZAY Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 139 page  Functional Overview 63 April 2004 − Revised January 2008 SPRS244J Table 3−29. GPIO (Continued) WORD ADDRESS RESET VALUE† DESCRIPTION PIN REGISTER NAME 0x4404 EHPIGPIODIR[5:0] GPIO[13:8] EHPI/GPIO Direction Register 0000 0000 0000 0000 0x4405 EHPIGPIODATA[5:0] GPIO[13:8] EHPI/GPIO Data Register 0000 0000 00xx xxxx † Hardware reset; x denotes a “don’t care.” Table 3−30. Device Revision ID WORD ADDRESS REGISTER NAME DESCRIPTION VALUE‡ 0x3803 Rev ID[4:1] Silicon Revision Identification Rev. 1.0: xxxx xxxx xxx0 001x ‡ x denotes a “don’t care.” Table 3−31. I2C Module Registers WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE† 0x3C00 I2COAR[9:0]§ I2C Own Address Register 0000 0000 0000 0000 0x3C01 I2CIER I2C Interrupt Enable Register 0000 0000 0000 0000 0x3C02 I2CSTR I2C Status Register 0000 0001 0000 0000 0x3C03 I2CCLKL[15:0] I2C Clock Divider Low Register 0000 0000 0000 0000 0x3C04 I2CCLKH[15:0] I2C Clock Divider High Register 0000 0000 0000 0000 0x3C05 I2CCNT[15:0] I2C Data Count 0000 0000 0000 0000 0x3C06 I2CDRR[7:0] I2C Data Receive Register 0000 0000 0000 0000 0x3C07 I2CSAR[9:0] I2C Slave Address Register 0000 0011 1111 1111 0x3C08 I2CDXR[7:0] I2C Data Transmit Register 0000 0000 0000 0000 0x3C09 I2CMDR[14:0] I2C Mode Register 0000 0000 0000 0000 0x3C0A I2CISRC I2C Interrupt Source Register 0000 0000 0000 0000 0x3C0B − Reserved 0x3C0C I2CPSC I2C Prescaler Register 0000 0000 0000 0000 0x3C0D − Reserved 0x3C0E − Reserved 0x3C0F I2CMDR2 I2C Mode Register 2 0000 0000 0000 0000 − I2CRSR I2C Receive Shift Register (not accessible to the CPU) − I2CXSR I2C Transmit Shift Register (not accessible to the CPU) † Hardware reset; x denotes a “don’t care.” § This register must be set by the user. The user may program the I2C’s own address to any value, as long as the value does not conflict with the I2C addresses of other components connected to the I2C bus. NOTE: I2C protocol compatible, no fail-safe buffer. Table 3−32. Watchdog Timer Registers WORD ADDRESS REGISTER NAME DESCRIPTION RESET VALUE† 0x4000 WDTIM[15:0] WD Timer Counter Register 1111 1111 1111 1111 0x4001 WDPRD[15:0] WD Timer Period Register 1111 1111 1111 1111 0x4002 WDTCR[13:0] WD Timer Control Register 0000 0011 1100 1111 0x4003 WDTCR2[15:0] WD Timer Control Register 2 0001 0000 0000 0000 † Hardware reset; x denotes a “don’t care.” |
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