Datasheet

10 of 25

V 2.21

www.infineon.com/soi

2020-07-07

2ED2182 (4) S06F (J)

650 V half-bridge gate driver with integrated bootstrap diode

5.3

Deadtime and matched propagation delays

This 2ED2182 (4) S06F (J) features integrated deadtime protection circuitry. The deadtime is fixed for

2ED2182S06F; is programmable for 2ED2182S06J, it provides greater design flexibility. The deadtime feature

inserts a time period (a minimum deadtime) in which both the high- and low-side power switches are held off;

this is done to ensure that the power switch being turned off has fully turned off before the second power switch

is turned on. This minimum deadtime is automatically inserter whenever the external deadtime is shorter than

DT; external deadtimes larger than DT are not modified by the gate driver. Figure 8 illustrates the deadtime

period and the relationship between the output gate signals.

The deadtime circuitry of 2ED2182 (4) S06F (J) is matched with respect to the high- and low-side outputs. Figure

9 defines the two deadtime parameters (i.e., DTLO-HO and DTHO-LO); the deadtime matching parameter (MDT)

associated with the 2ED2182S06F (J) specifies the maximum difference between DTLO-HO and DTHO-LO.

Figure 8

Dead Time Definitions

Figure 9

Delay Matching Waveform Definitions

The 2ED2182 (4) S06F (J) is designed with propagation delay matching circuitry. With this feature, the IC’s

both the low-side channels and the high-side channels; the maximum difference is specified by the delay

The 14-pin variant (2ED21824S06J) provides greater design flexibility with a programmable dead-time feature

using an external resistor (RDT) connected between the DT pin and VSS pin as shown in figure 10.

Figure 10

14-pin half-bridge variants having adjustable dead-time feature settable with a resistor

14

13

12

11

LIN

1

2

3

4

HO

DT

HIN

VSS

5

COM

6

LO

7

VCC

10

9

8

Up to 650V

TO LOAD

VCC

HIN

LIN

VSS

2ED21824S06J

LIN

HIN

HO

LO

12 V

3V

3V

12V

1.65V

1.65V

DT

DT