JS28F640J3A-150 datasheet(32/72 Pages) INTEL

32 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

9.0

Bus Operations

This section provides an overview of device bus operations. The on-chip Write State Machine

(WSM) manages all erase and program algorithms. The system CPU provides control of all in-

system read, write, and erase operations of the device via the system bus.

Device commands are written to the CUI to control all of the flash memory device’s operations.

The CUI does not occupy an addressable memory location; it’s the mechanism through which the

flash device is controlled.

9.1

Bus Operations Overview

The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash

memory conform to standard microprocessor bus cycles.

Table 12. Bus Operations

Mode

RP#

CE[2:0]

(1)

OE#

(2)

WE#

(2)

Address

VPEN

Data

(3)

STS

(default

mode)

Notes

Read Array

VIH

Enabled

VIL

VIH

DOUT

High Z

(7)

4,5,6

Output Disable

VIH

Enabled

VIH

High Z

Standby

VIH

Disabled

High Z

Reset/Power-Down

Mode

VIL

High Z

(7)

Read Identifier Codes

VIH

Enabled

VIL

VIH

See

Table 17

Note 8

High Z(7)

Read Query

VIH

Enabled

VIL

VIH

See

Table

10.3

Note 9

High Z

(7)

Read Status (WSM off)

VIH

Enabled

VIL

VIH

DOUT

Read Status (WSM on)

VIH

Enabled

VIL

VIH

D7 = DOUT

D[15:8] = High Z

D[6:0] = High Z

Write

VIH

Enabled

VIH

VIL

XVPENH

DIN

6,10,11

NOTES:

1. See Table 13 on page 33 for valid CE configurations.

2. OE# and WE# should never be enabled simultaneously.

3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high.

4. Refer to DC Characteristics. When VPEN ≤ VPENLK, memory contents can be read, but not altered.

5. X can be VIL or VIH for control and address signals, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and

VPENH voltages.

6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It

is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or

reset/power-down mode.

7. High Z will be VOH with an external pull-up resistor.

8. See Section 10.2, “Read Identifier Codes” on page 39 for read identifier code data.

9. See Section 10.3, “Read Query/CFI” on page 41 for read query data.

10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC

is within specification.

JS28F640J3A-150 Datasheet(PDF) 32 Page - Intel Corporation

JS28F640J3A-150 Datasheet(HTML) 32 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL