JS28F640J3A-150 datasheet(46/72 Pages) INTEL

46 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

13.0

Security Modes

This device offers both hardware and software security features. Block lock operations, PRs, and

VPEN allow the user to implement various levels of data protection. The following section

describes security features in detail.

Other security features are available that are not described in this datasheet. Please contact your

local Intel Field Representative for more information.

13.1

Set Block Lock-Bit

A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program

and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command.

This command is invalid while the WSM is running or the device is suspended.

Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with

appropriate block address is followed by either the set block lock-bit confirm (and an address

within the block to be locked). The WSM then controls the set lock-bit algorithm. After the

sequence is written, the device automatically outputs Status Register data when read (see Figure 24

on page 65). The CPU can detect the completion of the set lock-bit event by analyzing the STS

signal output or SR.7.

When the set lock-bit operation is complete, SR.4 should be checked. If an error is detected, the

Status Register should be cleared. The CUI will remain in Read Status Register mode until a new

command is issued.

This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally

set. An invalid Set Block Lock-Bit command will result in SR.4 and SR.5 being set. Also, reliable

operations occur only when VCC and VPEN are valid. With VPEN ≤ VPENLK, lock-bit contents are

protected against alteration.

13.2

Clear Block Lock-Bits

All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lock-

bits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while

the WSM is running or the device is suspended.

Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup

is first written. The device automatically outputs Status Register data when read (see Figure 25 on

page 66). The CPU can detect completion of the clear block lock-bits event by analyzing the STS

signal output or SR.7.

When the operation is complete, SR.5 should be checked. If a clear block lock-bit error is detected,

the Status Register should be cleared. The CUI will remain in Read Status Register mode until

another command is issued.

JS28F640J3A-150 Datasheet(PDF) 46 Page - Intel Corporation