JS28F640J3A-150 datasheet(33/72 Pages) INTEL

33 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

9.1.1

Bus Read Operation

To perform a bus read operation, CEx (refer to Table 13 on page 33) and OE# must be asserted.

CEx is the device-select control; when active, it enables the flash memory device. OE# is the data-

output control; when active, the addressed flash memory data is driven onto the I/O bus. For all

read states, WE# and RP# must be de-asserted. See Section 7.1, “Read Operations” on page 22.

Refer to Section 10.0, “Read Operations” on page 37 for details on reading from the flash array,

and refer to Section 14.0, “Special Modes” on page 50 for details regarding all other available read

states.

9.1.2

Bus Write Operation

Writing commands to the Command User Interface enables various modes of operation, including

the reading of array data, CFI data, identifier codes, inspection and clearing of the Status Register,

and, when VPEN = VPENH, block erasure, program, and lock-bit configuration.

The Block Erase command requires appropriate command data and an address within the block to

be erased. The Byte/Word Program command requires the command and address of the location to

be written. Set Block Lock-Bit commands require the command and block within the device to be

locked. The Clear Block Lock-Bits command requires the command and address within the device.

The CUI does not occupy an addressable memory location. It is written when the device is enabled

and WE# is active. The address and data needed to execute a command are latched on the rising

edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 on

page 33). Standard microprocessor write timings are used.

9.1.3

Output Disable

With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output

signals D[15:0] are placed in a high-impedance state.

Table 13. Chip Enable Truth Table

CE2

CE1

CE0

DEVICE

VIL

Enabled

VIL

VIH

Disabled

VIL

VIH

VIL

Disabled

VIL

VIH

Disabled

VIH

VIL

Enabled

VIH

VIL

VIH

Enabled

VIH

VIL

Enabled

VIH

Disabled

NOTE: For single-chip applications, CE2 and CE1 can be connected to VIL.

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