JS28F640J3A-150 datasheet(35/72 Pages) INTEL

35 / 72 page

256-Mbit J3 (x8/x16)

Datasheet

9.2

Device Commands

When the VPEN voltage ≤ VPENLK, only read operations from the Status Register, CFI, identifier

codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program,

and lock-bit configuration operations. Device operations are selected by writing specific

commands into the CUI. Table 14, “Command Bus-Cycle Definitions” on page 35 defines these

commands.

Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)

Command

Scalable or

Basic

Command

Set

(2)

Bus

Cycles

Req’d.

First Bus Cycle

Second Bus Cycle

Notes

Oper(3)

Addr(4)

Data(5,6)

Oper(3)

Addr(4)

Data(5,6)

Read Array

SCS/BCS

Write

0xFF

Read Identifier Codes

SCS/BCS

≥ 2

Write

0X90

Read

1,7

Read Query

SCS

≥ 2

Write

0x98

Read

Read Status Register

SCS/BCS

Write

0x70

Read

SRD

1,8

Clear Status Register

SCS/BCS

Write

0x50

Write to Buffer

SCS/BCS

> 2

Write

0xE8

Write

1,9, 10,

Word/Byte Program

SCS/BCS

Write

0x40 or

0x10

Write

1,12,13

Block Erase

SCS/BCS

Write

0x20

Write

0xD0

1,11,12

Block Erase, Program

Suspend

SCS/BCS

Write

0xB0

1,12,14

Block Erase, Program

Resume

SCS/BCS

Write

0xD0

1,12

Configuration

SCS

Write

0xB8

Write

Set Block Lock-Bit

SCS

Write

0x60

Write

0x01

JS28F640J3A-150 Datasheet(PDF) 35 Page - Intel Corporation

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