 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PIC16F916E/P301 Datasheet(PDF) 265 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
PIC16F916E/P301 Datasheet(HTML) 265 Page - Microchip Technology |
|
|
265 / 272 page  © 2005 Microchip Technology Inc. Preliminary DS41250E-page 263 PIC16F917/916/914/913 PIE2 (Peripheral Interrupt Enable 2)........................... 25 PIR1 (Peripheral Interrupt Register 1) ........................ 26 PIR2 (Peripheral Interrupt Register 2) ........................ 27 PORTA........................................................................ 32 PORTB........................................................................ 42 PORTC ....................................................................... 51 PORTD ....................................................................... 60 PORTE........................................................................ 65 RCSTA (Receive Status and Control)....................... 128 Reset Values............................................................. 192 Reset Values (Special Registers) ............................. 194 Special Function Register Map PIC16F913/916................................................... 15 PIC16F914/917................................................... 16 Special Register Summary Bank 0................................................................. 17 Bank 1................................................................. 18 Bank 2................................................................. 19 Bank 3................................................................. 20 SSPCON (Sync Serial Port Control) Register........... 161 SSPSTAT (Sync Serial Port Status) Register........... 160 Status.......................................................................... 21 T1CON (Timer1 Control)............................................. 87 T2CON (Timer2 Control)............................................. 90 TRISA (PORTA Tri-state) ........................................... 32 TRISB (PORTB Tri-state) ........................................... 42 TRISC (PORTC Tri-state) ........................................... 51 TRISD (PORTD Tri-state) ........................................... 60 TRISE (PORTE Tri-state) ........................................... 65 TXSTA (Transmit Status and Control) ...................... 127 VRCON (Voltage Reference Control) ....................... 100 WDTCON (Watchdog Timer Control) ....................... 200 WPUB (Weak Pull-up PORTB) ................................... 43 Reset................................................................................. 187 Revision History ................................................................ 257 S S (Start) bit ........................................................................ 160 SCI. See USART Serial Communication Interface. See USART. Slave Select Synchronization ........................................... 166 SMP bit ............................................................................. 160 Software Simulator (MPLAB SIM)..................................... 216 Special Function Registers ................................................. 14 SPI Mode .................................................................. 159, 166 Associated Registers ................................................ 168 Bus Mode Compatibility ............................................ 168 Effects of a Reset...................................................... 168 Enabling SPI I/O ....................................................... 164 Master Mode ............................................................. 165 Master/Slave Connection.......................................... 164 Serial Clock (SCK pin) .............................................. 159 Serial Data In (SDI pin) ............................................. 159 Serial Data Out (SDO pin) ........................................ 159 Slave Select .............................................................. 159 Slave Select Synchronization ................................... 166 Sleep Operation ........................................................ 168 SPI Clock .................................................................. 165 Typical Connection ................................................... 164 SSP Overview SPI Master/Slave Connection ................................... 164 SSP I2C Operation ............................................................ 169 Slave Mode ............................................................... 169 SSP Module Clock Synchronization and the CKP Bit.................... 175 SPI Master Mode...................................................... 165 SPI Slave Mode........................................................ 166 SSPBUF ................................................................... 165 SSPSR ..................................................................... 165 SSPEN bit......................................................................... 161 SSPM bits ......................................................................... 161 SSPOV bit ........................................................................ 161 Status Register ................................................................... 21 Synchronous Master Reception Associated Registers................................................ 140 Synchronous Master Transmission Associated Registers................................................ 139 Synchronous Serial Port Enable bit (SSPEN) .................. 161 Synchronous Serial Port Mode Select bits (SSPM).......... 161 Synchronous Serial Port. See SSP Synchronous Slave Reception Associated Registers................................................ 142 Synchronous Slave Transmission Associated Registers................................................ 142 T T1CON Register ................................................................. 87 Time-out Sequence .......................................................... 190 Timer0 Associated Registers.................................................. 83 External Clock ............................................................ 82 External Clock Requirements ................................... 234 Interrupt ...................................................................... 81 Operation .................................................................... 81 T0CKI ......................................................................... 82 Timer0 Module.................................................................... 81 Timer1 Associated Registers.................................................. 89 Asynchronous Counter Mode ..................................... 88 Reading and Writing ........................................... 88 External Clock Requirements ................................... 234 Interrupt ...................................................................... 86 Modes of Operations .................................................. 86 Operation During Sleep .............................................. 89 Prescaler .................................................................... 86 Resetting of Timer1 Registers .................................... 89 Resetting Timer1 Using a CCP Trigger Output .......... 88 Timer1 Gate Inverting Gate ..................................................... 86 Selecting Source .......................................... 86, 97 Synchronizing C2OUT w/ Timer1 ....................... 97 TMR1H Register......................................................... 85 TMR1L Register ......................................................... 85 Timer1 Module with Gate Control ....................................... 85 Timer2 ................................................................................ 90 Associated registers ................................................... 91 Operation .................................................................... 90 Postscaler................................................................... 90 PR2 Register .............................................................. 90 Prescaler .................................................................... 90 TMR2 Output .............................................................. 91 TMR2 Register ........................................................... 90 TMR2 to PR2 Match Interrupt............................... 90, 91 Timing Diagrams A/D Conversion ........................................................ 243 Asynchronous Master Transmission ........................ 132 Asynchronous Master Transmission (Back to Back) 132 Asynchronous Reception.......................................... 135 Asynchronous Reception with Address Byte First .... 137 Asynchronous Reception with Address Detect......... 137 Brown-out Reset (BOR)............................................ 232 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
