8 Detailed Description

8.1 Overview

The SN74HCS165 is a parallel- or serial-in, serial-out 8-bit shift register with Schmitt-trigger inputs.

This device has two modes of operation: load data, and shift data.

When the shift or load (SH/LD) input is held in the low state, the internal registers are loaded with data from the

eight lettered inputs (A-H). This operation is asynchronous. In this state, the output (Q) will have the same state

as the input H, while the inverted output (Q) will have the opposite state.

When the shift or load (SH/LD) input is held in the high state, the internal registers hold their current state until a

clock pulse is received. On the rising edge of the clock (CLK) input, data from the serial input will be loaded into

the first register, and the data in the internal registers will be shifted by one place. The last register will lose its

value. The output (Q) will always be in the same state as the last register, and the inverted output (Q) will have

the opposite state. The clock inhibit (CLK INH) input can be held high to prevent clock pulses from being

detected. CLK and CLK INH are interchangable inputs.

8.2 Functional Block Diagram

SH/LD

SER

CLK INH

CLK

A

D

S

R

Q

B

D

S

R

Q

5 Additional

Shift Register

Stages

C

D

E

F

G

H

D

S

R

Q

Q

Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS165

8.3 Feature Description

8.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink

and source similar currents. The drive capability of this device may create fast edges into light loads so routing

and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable

of driving larger currents than the device can sustain without being damaged. It is important for the output power

of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the

Absolute Maximum Ratings must be followed at all times.

Unused push-pull CMOS outputs should be left disconnected.

8.3.2 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are

typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table

from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the

Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics

table, using Ohm's law (R = V ÷ I).

SN74HCS165

SCLS828 – AUGUST 2020

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