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SN74HCS165 Datasheet(PDF) 11 Page - Texas Instruments |
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SN74HCS165 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 26 page ![]() The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. 8.3.3 Clamp Diode Structure The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical Placement of Clamping Diodes for Each Input and Output. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND Logic Input Output VCC Device -IIK +IIK +IOK -IOK Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output 8.3.4 Latching Logic This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip- flops, but include all logic circuits that act as volatile memory. When the device is powered on, the state of each latch is unknown. There is no default state for each latch at start-up. The output state of each latching logic circuit only remains stable as long as power is applied to the device within the supply voltage range specified in the Recommended Operating Conditions table. www.ti.com SN74HCS165 SCLS828 – AUGUST 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74HCS165 |
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