EKTF6708 datasheet(127/158 Pages) EMC

127 / 158 page

eKTF6708

8-Bit Microcontroller

IC Product Specification (V1.2) 03.12.2020

 117

(This specification is subject to change without prior notice)

The I2C interrupt occurs as describe below:

Condition

Master/Slave Transmit Address

Transmit Data

Stop

Master Transmitter

(transmits to

Slave-Receiver)

Master

Transmit interrupt Transmit interrupt

Slave

Receive interrupt

Stop interrupt

Master Receiver

(read Slave-

Transmitter)

Master

Transmit interrupt Receive interrupt

Slave

Transmit interrupt Transmit interrupt

Stop interrupt

Within the procedure of the

2C bus, unique situations could arise which are defined as

START (S) and STOP (P) conditions.

A HIGH to LOW transition on the SDA line while SCL is HIGH is one such unique case.

This situation indicates a START condition.

A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition.

SCL

SDA

START

STOP

change

of data

allowed

data line

stable;

data valid

Figure 6-12

2C Transfer Condition

6.12.1 7-Bit Slave Address

Master-transmitter transmits to Slave-receiver. The transfer direction is not changed.

Master reads Slave immediately after the first byte. At the moment of the first

acknowledgement, the Master-transmitter becomes a Master-receiver and the

Slave-receiver becomes a Slave-transmitter. This first acknowledgement is still generated

by the Slave. The STOP condition is generated by the Master, which has previously sent a

Not-Acknowledge (A). The only difference between Master-transmitter and

Master-receiver is their R//W bits. If the R//W bit is

“0”, the Master device would be a

transmitter. Otherwise, the Master device would be a receiver (R//W Bit =

“1”).

EKTF6708 Datasheet(PDF) 127 Page - ELAN Microelectronics Corp

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