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STM32G031F6 Datasheet(PDF) 85 Page - STMicroelectronics

Part # STM32G031F6
Description  Arm® Cortex®-M0 32-bit MCU, up to 64 KB Flash, 8 KB RAM, 2x USART, timers, ADC, comm. I/Fs, 1.7-3.6V
PDF  117 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32G031F6 Datasheet(HTML) 85 Page - STMicroelectronics

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DS12992 Rev 2
85/117
STM32G031x4/x6/x8
Electrical characteristics
92
5.3.21
Timer characteristics
The parameters given in the following tables are guaranteed by design. Refer to
Section 5.3.14: I/O port characteristics for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).
5.3.22
Characteristics of communication interfaces
I2C-bus interface characteristics
The I2C-bus interface meets timing requirements of the I2C-bus specification and user
manual rev. 03 for:
•
Standard-mode (Sm): with a bit rate up to 100 kbit/s
•
Fast-mode (Fm): with a bit rate up to 400 kbit/s
•
Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
Table 64. TIMx(1) characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)
Timer resolution time
-1
-
tTIMxCLK
fTIMxCLK = 64 MHz
15.625
-
ns
fEXT
Timer external clock frequency
on CH1 to CH4
-0
fTIMxCLK/2
MHz
fTIMxCLK = 64 MHz
0
40
ResTIM
Timer resolution
TIMx (except TIM2)
-
16
bit
TIM2
-
32
tCOUNTER
16-bit counter clock period
-
1
65536
tTIMxCLK
fTIMxCLK = 64 MHz
0.015625
1024
µs
tMAX_COUNT
Maximum possible count with
32-bit counter
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 64 MHz
-
67.10
s
1. TIMx, is used as a general term in which x stands for 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17.
Table 65. IWDG min/max timeout period at 32 kHz LSI clock(1)
Prescaler divider
PR[2:0] bits
Min timeout RL[11:0]= 0x000
Max timeout RL[11:0]= 0xFFF
Unit
/4
0
0.125
512
ms
/8
1
0.250
1024
/16
2
0.500
2048
/32
3
1.0
4096
/64
4
2.0
8192
/128
5
4.0
16384
/256
6 or 7
8.0
32768
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.



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