STM32G031F6 datasheet(21/117 Pages) STMICROELECTRONICS

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DS12992 Rev 2

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STM32G031x4/x6/x8

Functional overview

clock failure can also be detected and generate an interrupt. The CCS feature can be

enabled by software.

•

Clock output:

–

MCO (microcontroller clock output) provides one of the internal clocks for

external use by the application

–

LSCO (low speed clock output) provides LSI or LSE in all low-power modes

(except in VBAT operation).

Several prescalers allow the application to configure AHB and APB domain clock

frequencies, 64 MHz at maximum.

3.10

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of

the GPIO pins are shared with special digital or analog functions.

Through a specific sequence, this special function configuration of I/Os can be locked, such

as to avoid spurious writing to I/O control registers.

3.11

Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with

single-AHB architecture.

With 5 channels, it performs data transfers between memory-mapped peripherals and/or

memories, to offload the CPU.

Each channel is dedicated to managing memory access requests from one or more

peripherals. The unit includes an arbiter for handling the priority between DMA requests.

Main features of the DMA controller:

•

Single-AHB master

•

Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-

peripheral data transfers

•

Access, as source and destination, to on-chip memory-mapped devices such as Flash

memory, SRAM, and AHB and APB peripherals

•

All DMA channels independently configurable:

–

Each channel is associated either with a DMA request signal coming from a

peripheral, or with a software trigger in memory-to-memory transfers. This

configuration is done by software.

–

Priority between the requests is programmable by software (four levels per

channel: very high, high, medium, low) and by hardware in case of equality (such

as request to channel 1 has priority over request to channel 2).

–

Transfer size of source and destination are independent (byte, half-word, word),

emulating packing and unpacking. Source and destination addresses must be

aligned on the data size.

–

Support of transfers from/to peripherals to/from memory with circular buffer

management

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