TMP47C101 datasheet(16/32 Pages) TOSHIBA

16 / 32 page

16/32

TOSHIBA CORPORATION

TMP47C101/201

The warm-up time is obtained by dividing the basic

clock by the interval timer, so that, if the frequency at

releasing the hold operation is unstable, the warm-up

time shown in Figure 2-18. includes an error. There-

fore, the warm-up time must be handled as an approx-

imate value. The hold operation is also released by

setting the RESET pin to the low level. In this case, the

normal reset operation follows immediately.

Note:

To release the hold operation at a low hold voltage, the following

points must be considered:

When the power voltage rises from the hold voltage to the operat-

ing voltage, the RESET pin input is also at the high level and its

voltage rises with the power voltage.

In this case, if a time-constant circuit or the like is

externally attached, the voltage rise of the RESET pin

input occurs after the power voltage rise. If the voltage

level of the RESET pin input gets under the non-

inverted high input voltage of the RESET pin input (the

hysteresis input), a reset operation may happen.

2.8 Interrupt Function

2.8.1 Interrupt Controller

There are 5 interrupt sources (2 external and 3 internal). The

prioritized multiple interrupt capability is supported. The inter-

rupt latches (IL5 through IL0) to hold interrupt requests are pro-

vided for the interrupt sources. Each interrupt latch is set to “1”

when an interrupt request is made, asking the CPU to accept

the interrupt. The acceptance of interrupt can be permitted or

prohibited by program through the interrupt enable master ﬂip-

ﬂop (EIF) and interrupt enable register (EIR). When two or more

interrupts occur simultaneously, the one with the highest prior-

ity determined by hardware is serviced ﬁrst.

Table 2-2. Interrupt Sources

TMP47C101 Datasheet(PDF) 16 Page - Toshiba Semiconductor