TMP47C101 datasheet(25/32 Pages) TOSHIBA

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TOSHIBA CORPORATION

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TMP47C101/201

The timer/counter increments at the rising edge of each

count pulse. Counting starts with the first rising edge of the

count pulse generated after the command has been set.

Count operation is performed in one instruction cycle after the

current instruction execution, during which the execution of a

next instruction and the acceptance of an interrupt are de-

layed. If counting is requested by both TC1 and TC2 simulta-

neously, the request by TC1 is preferred. The request by TC2

is accepted in the next instruction cycle. Therefore, during

count operation, the apparent instruction execution speed

drops as counting occurs more frequently.

The timer/counter causes an interrupt upon occurrence of an

overﬂow (a transition of the count value from FFFH to 000H). If

the timer/counter is in the interrupt enabled state and the over-

ﬂow interrupt is accepted immediately after its occurrence, the

interrupt is processed in the sequence shown in Figure 3-8.

Note that counting continues if there is a count request after

overﬂow occurrence.

Figure 3-8. Timer/Counter Overﬂow Interrupt Timing

(1)

Event counter mode

In the event counter mode, the timer/counter incre-

ments at each rising edge of the external pin (T2) input.

The maximum applied frequency of the external pin

input is fc/32. The apparent instruction execution

speed drops most to (1/3) x 100 = 33% when TC2 is

operated at the maximum applied frequency because

the count operation is inserted once every 4 instruction

cycles. For example, the instruction execution speed

of 2

µs drops to 2.66µs

Example: To operate TC2 in the event counter mode.

A, #0100B

; OP1D

←01**

OUT

A, %0P1D

Figure 3-9. Event Counter Timing Chart

(2)

Timer mode

In the timer mode, the timer/counter increments at the

rising edge of the internal pulse generated from the

timing generator. One of 4 internal pulse rates can be

selected by the command register. The selected rate

can be initially set to the timer/counter to generate an

overﬂow interrupt in order to create a desired time

interval.

When an internal pulse rate of fc/210 is used, a count

operation is inserted once every 128 instruction cycles,

so that the apparent instruction execution speed drops

by (1/127) x 100 = 0.8%. For example, the instruction

execution speed of 2

µs drops to 2.016µs.

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