AM6421 datasheet(164/237 Pages) TI

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NO.

PARAMETER

MODE

(3)

MIN

MAX UNIT

GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn

invalid to output chip select GPMC_CSn[i](2)

invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+G

2+G

GNF7 tw(aleH-wenV)

Delay time, output address valid and address latch

enable GPMC_ADVn_ALE high to output write

enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+C

2+C

GNF8 tw(wenIV-aleIV)

Delay time, output write enable GPMC_WEn

invalid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+F

2+F

GNF9 tc(wen)

Cycle time, write

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0+H

GNF10 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](2)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+I

2+I

GNF13 tw(oenV)

Pulse duration, output enable GPMC_OEn_REn

valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0+K

GNF14 tc(oen)

Cycle time, read

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0+L

GNF15 tw(oenIV-CSn[i]V)

Delay time, output enable GPMC_OEn_REn

invalid to output chip select GPMC_CSn[i](2)

invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+M

2+M

(1)

A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK

(2)

In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

(3)

For div_by_1_mode:

•

GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:

–

GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:

•

CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33 MHz

For TIMEPARAGRANULARITY_X1:

•

GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/

WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,

OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)

GPMC_FCLK

GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADCn_ALE

GPMC_OEn_REn

GPMC_WEn

GPMC_AD[15:0]

Command

GNF0

GNF1

GNF2

GNF3

GNF4

GNF5

GNF6

GPMC_12

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 7-48. GPMC and NAND Flash — Command Latch Cycle

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

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