AM6421 datasheet(224/237 Pages) TI

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Device

USBn_VBUS

J7ES_USB_VBUS_01

VSS

16.5 kΩ

10 kΩ

3.5 kΩ

VBUS signal

(BZX84C6V8 or equivalent)

6.8V

Figure 9-4. USB VBUS Detect Voltage Divider / Clamp Circuit

The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 9-4 limits the input

current to the actual device pin in a case where VBUS is applied while the device is powered off.

9.3.4 System Power Supply Monitor Design Guidelines

The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically a

single pre-regulated power source for the entire system. This supply is monitored by comparing the output of an

external voltage divider circuit sourced by this supply with an internal voltage reference, with a power fail event

being triggered when the voltage applied to VMON_VSYS drops below the internal reference voltage. The actual

system power supply voltage trip point is determined by the system designer when selecting component values

used to implement the external resistor voltage divider circuit.

When designing the resistor divider circuit it is important to understand various factors which contribute to

variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of the

VMON_VSYS input threshold which has a nominal value of 0.45 V, with a variation of ±3%. Precision 1%

resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider. This

minimizes variability contributed by resistor value tolerances. Input leakage current associated with

VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the

voltage divider output. The VMON_VSYS input leakage current may be in the range of 10 nA to 2.5 µA when

applying 0.45 V.

Note

The resistor voltage divider shall be designed such that its output voltage never exceeds the

maximum value defined in Section 7.4, Recommended Operating Conditions, during normal operating

conditions.

Figure 9-5 presents an example, where the system power supply is nominally 5 V and the maximum trigger

threshold is 5 V - 10%, or 4.5 V.

For this example, it is important to understand which variables effect the maximum trigger threshold when

selecting resistor values. It is obvious a device which has a VMON_VSYS input threshold of 0.45 V + 3% needs

to be considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The

effect of resistor tolerance and input leakage also needs to be considered, but how these contributions effect the

maximum trigger point may not be obvious. When selecting component values which produce a maximum

trigger voltage, the system designer must consider a condition where the value of R1 is 1% low and the value of

R2 is 1% high combined with a condition where input leakage current for the VMON_VSYS pin is 2.5 µA. When

implementing a resistor divider where R1 = 4.81 KΩ and R2 = 40.2 KΩ, the result is a maximum trigger threshold

of 4.523 V.

Once component values have been selected to satisfy the maximum trigger voltage as described above, the

system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

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