AD9546SLASHPCBZ datasheet(105/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 105 of 205

DISTRIBUTION EMBEDDED OUTPUT CLOCK MODULATION

MODULATION CONTROLLER OVERVIEW

The AD9546 has the capability to embed a low frequency clock

within a high frequency carrier. Referring to Figure 68, only the

primary output of a Q divider pair routes to the modulation

controller, whereas the secondary output bypasses the modulation

controller and routes directly to the N shot/PRBS controller. Thus,

only the primary distribution clock outputs support embedded

clock modulation capability (for example, Output OUT0AP

supports modulation, whereas Output OUT0AN does not).

Embedded clock modulation consists of changing the pulse

width of the designated Q divider output clock in synchrony

with a binary modulation signal to produce modulation events.

A modulation event always spans two Q divider clock cycles

where the first clock cycle changes duty cycle, but the second

clock cycle may or may not change duty cycle (see the Balanced

and Unbalanced Modulation section).

An expanded diagram of the modulation controller appears in

Figure 74. Although Figure 74 is specific to PLL0, it is also

representative of PLL1, because there is a dedicated modulation

controller for each PLL channel.

Any one or more Q divider outputs with a single-letter

subscript (for example, Q0A but not Q0AA) can operate as an

embedded clock modulator. To enable embedded modulation,

use Bit 0 of the registers shown in Table 70.

Table 70. Enable Embedded Modulation Register Address

Q Divider

Q0A

0x10CF

Q0B

0x10D0

Q0C

0x10D1

Q1A

0x14CF

Q1B

0x14D0

Logic 1 selects the designated Q divider for embedded clock

modulation, whereas Logic 0 (default) bypasses the modulation

controller (via the mux in Figure 74).

Modulation control consists of two parameters: Δt and tMOD.

Parameter Δt defines the desired magnitude of the modulation

edge variation, and tMOD defines the modulation period (see

Figure 75). The modulated signal consists of a time step of

magnitude Δt occurring at regular intervals of period, tMOD. The

magnitude parameter, Δt, is common to all the modulators

within a PLL channel, whereas the period parameter, tMOD, is

unique to each modulator.

MODULATION MAGNITUDE

To set the modulation magnitude, use the 16-bit unsigned

integer (modulation step) in Register 0x10C0 to Register 0x10C1

for PLL0 and Register 0x14C0 to Register 0x14C1 for PLL1.

The modulation step value carries units of one-half of the

period of the input clock to the Q divider associated with the

modulator, yielding the following relationship:

D = Modulation Step/(2 × Qxy)

(3)

where:

D is the duty cycle deviation (that is, the time deviation of the

modulation edge from nominal, normalized to the Q divider

output period). Figure 75 shows D as Δt/tQ.

Qxy is the divide ratio of the relevant Q divider (x is 0 or 1, and

y is A, B or C).

Because the modulation step is common to all the modulators

in a PLL channel, whereas Qxy is unique to each Q divider, D

in Equation 3 is not necessarily the same for all the modulators

in a PLL channel.

Given the divide ratio for Q divider Q0A is 1001, find the

modulation step bit field value necessary for Modulator A to

yield 5% modulation.

Modulation of 5% implies D = 0.05. Substituting the

appropriate values into Equation 3 yields

0.05 = Modulation Step/(2 × 1001)

Therefore,

Modulation Step = 100 (rounded to nearest integer)

= 0x64 (hexadecimal)

Given the same modulation step value as in the preceding

example (modulation step = 100), find the modulation magnitude

for Modulator B assuming Q0B has a divide ratio of 8025.5.

D = Modulation Step/(2 × Qxy)

= 100/(2 × 8025.5)

= 0.00623 (0.623%)

AD9546/PCBZ Datasheet(PDF) 105 Page - Analog Devices

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