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ATMEGA640 Datasheet(PDF) 153 Page - Microchip Technology |
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ATMEGA640 Datasheet(HTML) 153 Page - Microchip Technology |
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153 / 436 page  153 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A Figure 17-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOVn Flag at BOTTOM. Figure 17-12. Timer/Counter Timing Diagram, no Prescaling Figure 17-13 shows the same timing data, but with the prescaler enabled. Figure 17-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) TOVn (FPWM) and ICFn (if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk Tn (clk I/O/1) clk I/O TOVn(FPWM) and ICF n(if used as TOP) OCRnx (Update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx Value New OCRnx Value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) |
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