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ATMEGA640 Datasheet(PDF) 155 Page - Microchip Technology

Part # ATMEGA640
Description  8-bit Microcontroller with 16/32/64KB In-System Programmable Flash
PDF  436 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ATMEGA640 Datasheet(HTML) 155 Page - Microchip Technology

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
DS40002211A
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the counting sequence of the
counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see
Table 17-2 on page 145. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter),
Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. For more
information on the different modes, see “Modes of Operation” on page 144.
Table 17-4 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast PWM mode.
Note:
A special case occurs when OCRnA/OCRnB/OCRnC equals TOP and COMnA1/COMnB1/COMnC1 is set. In this
case the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 146. for
more details.
Table 17-5 shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase correct and fre-
quency correct PWM mode.
Table 17-3.
Compare Output Mode, non-PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC disconnected
0
1
Toggle OCnA/OCnB/OCnC on compare match
1
0
Clear OCnA/OCnB/OCnC on compare match (set output to low level)
1
1
Set OCnA/OCnB/OCnC on compare match (set output to high level)
Table 17-4.
Compare Output Mode, Fast PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC disconnected
01
WGM13:0 = 14 or 15: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal
port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C
disconnected
10
Clear OCnA/OCnB/OCnC on compare match, set OCnA/OCnB/OCnC at BOTTOM (non-inverting
mode)
11
Set OCnA/OCnB/OCnC on compare match, clear OCnA/OCnB/OCnC at BOTTOM (inverting
mode)
Table 17-5.
Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
COMnA1
COMnB1
COMnC1
COMnA0
COMnB0
COMnC0
Description
0
0
Normal port operation, OCnA/OCnB/OCnC disconnected
01
WGM13:0 =9 or 11: Toggle OC1A on Compare Match, OC1B and OC1C disconnected (normal port
operation). For all other WGM1 settings, normal port operation, OC1A/OC1B/OC1C disconnected
10
Clear OCnA/OCnB/OCnC on compare match when up-counting
Set OCnA/OCnB/OCnC on compare match when downcounting
11
Set OCnA/OCnB/OCnC on compare match when up-counting
Clear OCnA/OCnB/OCnC on compare match when downcounting



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