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ATMEGA640 Datasheet(PDF) 158 Page - Microchip Technology

Part # ATMEGA640
Description  8-bit Microcontroller with 16/32/64KB In-System Programmable Flash
PDF  436 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

ATMEGA640 Datasheet(HTML) 158 Page - Microchip Technology

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]
DS40002211A
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
• Bit 5 – FOCnC: Force Output Compare for Channel C
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM mode. When writ-
ing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare match is forced on the waveform
generation unit. The OCnA/OCnB/OCnC output is changed according to its COMnx1:0 bits setting. Note that the
FOCnA/FOCnB/FOCnC bits are implemented as strobes. Therefore it is the value present in the COMnx1:0 bits
that determine the effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Com-
pare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
• Bit 4:0 – Reserved Bits
These bits are reserved for future use. For ensuring compatibility with future devices, these bits must be written to
zero when TCCRnC is written.
17.11.13 TCNT1H and TCNT1L – Timer/Counter 1
17.11.14 TCNT3H and TCNT3L – Timer/Counter 3
17.11.15 TCNT4H and TCNT4L –Timer/Counter 4
17.11.16 TCNT5H and TCNT5L –Timer/Counter 5
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct access, both for read
and for write operations, to the Timer/Counter unit 16-bit counter. To ensure that both the high and low bytes are
read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. See
“Accessing 16-bit Registers” on page 135.
Bit
7
65
43
2
1
0
(0x85)
TCNT1[15:8]
TCNT1H
(0x84)
TCNT1[7:0]
TCNT1L
Read/Write
R/WR/W
R/WR/W
R/WR/W
R/WR/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
65
43
2
1
0
(0x95)
TCNT3[15:8]
TCNT3H
(0x94)
TCNT3[7:0]
TCNT3L
Read/Write
R/WR/W
R/WR/W
R/WR/W
R/WR/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
65
43
2
1
0
(0xA5)
TCNT4[15:8]
TCNT4H
(0xA4)
TCNT4[7:0]
TCNT4L
Read/Write
R/WR/W
R/WR/W
R/WR/W
R/WR/W
Initial Value
0
0
0
0
0
0
0
0
Bit
7
65
43
2
1
0
(0x125)
TCNT5[15:8]
TCNT5H
(0x124)
TCNT5[7:0]
TCNT5L
Read/Write
R/WR/W
R/WR/W
R/WR/W
R/WR/W
Initial Value
0
0
0
0
0
0
0
0



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