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ATMEGA640 Datasheet(PDF) 162 Page - Microchip Technology |
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ATMEGA640 Datasheet(HTML) 162 Page - Microchip Technology |
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162 / 436 page  162 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register • Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the ICFn Flag, located in TIFRn, is set. • Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter- rupts” on page 101) is executed when the OCFnC Flag, located in TIFRn, is set. • Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter- rupts” on page 101) is executed when the OCFnB Flag, located in TIFRn, is set. • Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see “Inter- rupts” on page 101) is executed when the OCFnA Flag, located in TIFRn, is set. • Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector (see “Interrupts” on page 101) is executed when the TOVn Flag, located in TIFRn, is set. 17.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register 17.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register 17.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register Bit 76543 2 1 0 (0x73) – –ICIE5 – OCIE5C OCIE5B OCIE5A TOIE5 TIMSK5 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 00000 0 0 0 Bit 7 65 43 2 1 0 0x16 (0x36) – –ICF1 – OCF1C OCF1B OCF1A TOV1 TIFR1 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 2 1 0 0x18 (0x38) – –ICF3 – OCF3C OCF3B OCF3A TOV3 TIFR3 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 2 1 0 0x19 (0x39) – –ICF4 – OCF4C OCF4B OCF4A TOV4 TIFR4 Read/Write R R R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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