IMXRT1024IEC datasheet(4/90 Pages) NXP

4 / 90 page

i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020

NXP Semiconductors

i.MX RT1024 introduction

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Temperature sensor with programmable trip points

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GPC hardware power management controller

The i.MX RT1024 processors support the following system debug:

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Arm CortexM7 CoreSight debug and trace architecture

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Trace Port Interface Unit (TPIU) to support off-chip real-time trace

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Support for 5-pin (JTAG) and SWD debug interfaces selected by eFuse

Security functions are enabled and accelerated by the following hardware:

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High Assurance Boot (HAB)

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Data Co-Processor (DCP):

— AES-128, ECB, and CBC mode

— SHA-1 and SHA-256

— CRC-32

•

Bus Encryption Engine (BEE)

— AES-128, ECB, and CTR mode

— On-the-fly QSPI Flash decryption

•

True random number generation (TRNG)

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Secure Non-Volatile Storage (SNVS)

— Secure real-time clock (RTC)

— Zero Master Key (ZMK)

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Secure JTAG Controller (SJC)

NOTE

The actual feature set depends on the part numbers as described in Table 2.

Functions such as display and camera interfaces, connectivity interfaces,

and security features are not offered on all derivatives.

IMXRT1024IEC Datasheet(PDF) 4 Page - NXP Semiconductors