IMXRT1024IEC datasheet(53/90 Pages) NXP

53 / 90 page

Electrical characteristics

i.MX RT1024 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 11/2020

NXP Semiconductors

Figure 31. SPDIF_ST_CLK timing diagram

4.7

Analog

The following sections provide information about analog interfaces.

4.7.1

DCDC

Table 49 introduces the DCDC electrical specification.

4.7.2

A/D converter

This section introduces information about A/D converter.

Table 49. DCDC electrical specifications

Mode

Buck mode only, one output

Notes

Input voltage

3.3 V

± 10%

Output voltage

1.1 V

Configurable 0.8 ~ 1.575 with 25 mV one step

Max loading

500 mA

—

Loading in low power modes

200

A ~ 30 mA

—

Efficiency

90% max

@150 mA

Low power mode

Open loop mode

Ripple is about 15 mV

Run mode

• Always continuous mode

• Support discontinuous mode

Configurable by register

Inductor

4.7

H—

Capacitor

F—

Over voltage protection

1.6 V

Detect VDDSOC, when the voltage is higher

than 1.6 V, shutdown DCDC.

Over Current protection

1 A

Detect the peak current

• Run mode: when the current is larger than

1 A, shutdown DCDC.

• Stop mode: when the current is larger than

250 mA, stop charging the inductor.

Low battery detection

2.6 V

Detect the battery, when battery is lower than

2.6 V, shutdown DCDC.

SPDIF_ST_CLK

(Input)

stclkp

stclkph

stclkpl

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