COP8CFE9 datasheet(52/63 Pages) NSC

52 / 63 page

13.0 Instruction Set (Continued)

If Equal (IFEQ)

If Not Equal (IFNE)

If Greater Than (IFGT)

If Carry (IFC)

If Not Carry (IFNC)

If Bit (IFBIT)

If B Pointer Not Equal (IFBNE)

And Skip if Zero (ANDSZ)

Decrement Register and Skip if Zero (DRSZ)

13.4.9 No-Operation Instruction

The no-operation instruction does nothing, except to occupy

space in the program memory and time in execution.

No-Operation (NOP)

Note: The VIS is a special case of the Indirect Transfer of

Control addressing mode, where the double byte vector

associated with the interrupt is transferred from adjacent

addresses in the program memory into the program counter

(PC) in order to jump to the associated interrupt service

routine.

13.5 REGISTER AND SYMBOL DEFINITION

The following abbreviations represent the nomenclature

used in the instruction description and the COP8 cross-

assembler.

Registers

8-Bit Accumulator Register

8-Bit Address Register

Registers

8-Bit Segment Register

8-Bit Stack Pointer Register

15-Bit Program Counter Register

Upper 7 Bits of PC

Lower 8 Bits of PC

1 Bit of PSW Register for Carry

1 Bit of PSW Register for Half Carry

GIE

1 Bit of PSW Register for Global Interrupt

Enable

Interrupt Vector Upper Byte

Interrupt Vector Lower Byte

Symbols

[B]

Memory Indirectly Addressed by B Register

[X]

Memory Indirectly Addressed by X Register

Direct Addressed Memory

Mem

Direct Addressed Memory or [B]

Meml

Direct Addressed Memory or [B] or

Immediate Data

Imm

8-Bit Immediate Data

Reg

(Includes B, X and SP)

Bit

Bit Number (0 to 7)

←

Loaded with

↔

Exchanged with

COP8CFE9 Datasheet(PDF) 52 Page - National Semiconductor (TI)

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