COP8CFE9 datasheet(8/63 Pages) NSC

8 / 63 page

2.0 Electrical Characteristics (Continued)

TABLE 1. DC Electrical Characteristics (−40˚C

≤ T

A ≤ +85˚C) (Continued)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

Input Capacitance

7pF

Voltage on G6 to Force Execution from Boot

ROM(Note 8)

G6 rise time must be slower

than 100 ns

2xV

CC +7

G6 Rise Time to Force Execution from Boot ROM

100

Input Current on G6 when Input > V

IN =11V,VCC = 5.5V

500

µA

Flash Memory Data Retention

25˚C

100

yrs

Flash Memory Number of Erase/Write Cycles

See

Table 14, Typical Flash

Memory Endurance

cycles

AC Electrical Characteristics (−40˚C

≤ T

A ≤ +85˚C)

Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis.

Parameter

Conditions

Min

Typ

Max

Units

Instruction Cycle Time (t

Crystal/Resonator

4.5V

≤ V

CC ≤ 5.5V

0.5

µs

2.7V

≤ V

CC < 4.5V

1.5

µs

Flash Memory Page Erase Time

See

Table 14, Typical

Flash Memory

Endurance

1ms

Flash Memory Mass Erase Time

Frequency of MICROWIRE/PLUS in

Slave Mode

MHz

MICROWIRE/PLUS Setup Time (t

UWS)20

MICROWIRE/PLUS Hold Time (t

UWH)20

MICROWIRE/PLUS Output Propagation

Delay (t

UPD)

150

Input Pulse Width

Interrupt Input High Time

Interrupt Input Low Time

Timer 1 Input High Time

Timer 1 Input Low Time

Timer 2 Input High Time (Note 6)

MCLK or t

Timer 2 Input Low Time (Note 6)

MCLK or t

Output Pulse Width

Timer 2 Output High Time

150

Timer 2 Output Low Time

150

Reset Pulse Width

tC = instruction cycle time.

Note 2: Maximum rate of voltage change must be < 0.5 V/ms.

Note 3: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to VCC

and outputs driven low but not connected to a load.

Note 4: The HALT mode will stop CKI from oscillating. Measurement of IDD HALT is done with device neither sourcing nor sinking current; with A. B, G0, G2–G5,

H and L programmed as low outputs and not driving a load; all inputs tied to VCC; A/D converter and clock monitor and BOR disabled. Parameter refers to HALT

mode entered via setting bit 7 of the G Port data register.

Note 5: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > VCC and the pins will have sink current to VCC when

biased at voltages > VCC (the pins do not have source current when biased at a voltage below VCC). These two pins will not latch up. The voltage at the pins must

be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning excludes ESD transients.

Note 6: If timer is in high speed mode, the minimum time is 1 MCLK. If timer is not in high speed mode, the minimum time is 1 tC.

Note 7: Absolute Maximum Ratings should not be exceeded.

Note 8: Vcc must be valid and stable before G6 is raised to a high voltage.

COP8CFE9 Datasheet(PDF) 8 Page - National Semiconductor (TI)

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