A6986ITR datasheet(60/62 Pages) STMICROELECTRONICS

60 / 62 page

List of figures

Figure 1.

Application schematic ............................................................... 2

Figure 2.

Pin connection (top view) ............................................................. 3

Figure 3.

Circuit RVCC, RGND ................................................................. 7

Figure 4.

Iso-buck general schematic ........................................................... 9

Figure 5.

Internal block diagram .............................................................. 10

Figure 6.

Internal circuit.................................................................... 11

Figure 7.

Iso-buck basic operating principle ...................................................... 12

Figure 8.

Iso-buck primary and secondary current waveforms ......................................... 13

Figure 9.

Soft-start phase .................................................................. 14

Figure 10.

Enable the device with external voltage step............................................... 15

Figure 11.

Tracked soft-start at secondary side .................................................... 15

Figure 12.

Simulation with insufficient masking time (< 100 ns) ......................................... 16

Figure 13.

Simulation with appropriate masking time (330 ns) .......................................... 16

Figure 14.

Remaining oscillations filtered by the masking time and RC snubber circuit VIN = 12 V, N = 1.58, IOUTiso = 100 mA

.............................................................................. 16

Figure 15.

Schematic used for line and load regulation tests ........................................... 17

Figure 16.

Primary line regulation .............................................................. 17

Figure 17.

Secondary output line regulation ....................................................... 18

Figure 18.

Secondary winding current at different input voltages......................................... 18

Figure 19.

Load regulation of the non isolated output ................................................ 19

Figure 20.

Effect of the transformer leakage inductance on the isolated output load regulation .................... 19

Figure 21.

Input voltage effect on the load regulation of the isolated voltage................................. 20

Figure 22.

Valley current sense operation in short-circuit .............................................. 21

Figure 23.

Peak current sense operation in overcurrent condition ........................................ 21

Figure 24.

Peak currents depending on the secondary output current (VIN = 12 V, VOUT_pri = 5.3, N = 6, fSW = 500 kHz, no

primary output current) ............................................................. 22

Figure 25.

Overvoltage operation .............................................................. 23

Figure 26.

Block diagram of the loop ........................................................... 24

Figure 27.

Transconductance embedded error amplifier .............................................. 25

Figure 28.

Leading network example ........................................................... 26

Figure 29.

Bode plote (magnitude) ............................................................. 27

Figure 30.

Bode plot (phase) ................................................................. 28

Figure 31.

A6986I application circuit ............................................................ 29

Figure 32.

Isolated voltage variation due to the primary output current .................................... 30

Figure 33.

Secondary output maximum current .................................................... 30

Figure 34.

Voltage supervisor operation ......................................................... 31

Figure 35.

Voltage supervisor operation during OVP ................................................. 31

Figure 36.

Input RMS current................................................................. 32

Figure 37.

Two regulators not synchronized....................................................... 33

Figure 38.

Two regulators not synchronized....................................................... 33

Figure 39.

A6986I synchronization driving capability ................................................. 34

Figure 40.

Slave-to-master mode transition ....................................................... 35

Figure 41.

Master driving capability to synchronize the A6986I .......................................... 35

Figure 42.

Input capacitor AC current ........................................................... 36

Figure 43.

Primary (blue) winding current, secondary (pink) winding current and magnetizing current (black) .......... 39

Figure 44.

Secondary winding positive peak current dependency on duty cycle (IOUT_sec = 100 mA)................ 40

Figure 45.

Primary negative peak current dependency on duty cycle (VOUT_pri = 5 V, IOUT_pri = 0, IOUT_sec = 100 mA, N = 6,

fSW = 500 kHz, L = 19 µH) ........................................................... 40

Figure 46.

Secondary winding current according to different leakage inductances (simulation) .................... 41

Figure 47.

Snubber circuit ................................................................... 41

Figure 48.

Transformer parasitic capacitances ..................................................... 42

Figure 49.

Typical schematic with load applied to both the isolated and not isolated outputs...................... 43

A6986I

List of figures

DS13481 - Rev 2

page 60/62

A6986ITR Datasheet(PDF) 60 Page - STMicroelectronics

A6986ITR Datasheet(HTML) 60 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL