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STM32H723VG Datasheet(PDF) 148 Page - STMicroelectronics

Part # STM32H723VG
Description  32-bit Arm® Cortex®-M7 550 MHz MCU, up to 1 MB Flash memory, 564 KB RAM, 35 comms peripherals and analog interfaces
PDF  227 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32H723VG Datasheet(HTML) 148 Page - STMicroelectronics

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Electrical characteristics
STM32H723xE/G
148/227
DS13313 Rev 2
Table 71. SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tw(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck –
0.5
2Tfmc_ker_ck
+0.5
ns
tsu(SDCLKH _Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
1.5
-
td(SDCLKL_Add)
Address valid time
-
2.0
td(SDCLKL- SDNE)
Chip select valid time
-
1.5(2)
2. Using PC2_C I/O adds 4.5 ns to this timing.
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS)
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
2.0
th(SDCLKL_SDNCAS)
SDNCAS hold time
0.5
-
Table 72. LPSDR SDRAM read timings(1)
1. Guaranteed by characterization results.
Symbol
Parameter
Min
Max
Unit
tW(SDCLK)
FMC_SDCLK period
2Tfmc_ker_ck –
0.5
2Tfmc_ker_ck+0.5
ns
tsu(SDCLKH_Data)
Data input setup time
3
-
th(SDCLKH_Data)
Data input hold time
2.5
-
td(SDCLKL_Add)
Address valid time
-
2
td(SDCLKL_SDNE)
Chip select valid time
-
1.5(2)(3)
2. Using PC2 I/O adds 4 ns to this timing.
3. Using PC2_C I/O adds 16.5 ns to this timing.
th(SDCLKL_SDNE)
Chip select hold time
0
-
td(SDCLKL_SDNRAS
SDNRAS valid time
-
1
th(SDCLKL_SDNRAS)
SDNRAS hold time
0
-
td(SDCLKL_SDNCAS)
SDNCAS valid time
-
2
th(SDCLKL_SDNCAS)
SDNCAS hold time
0.5
-



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