STM32H723VG datasheet(152/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

152/227

DS13313 Rev 2

Figure 33. OCTOSPI DTR mode timing diagram

Table 76. OCTOSPI characteristics in DTR mode (no DQS)(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

FCK(3)

OCTOSPI clock frequency

1.71 V < VDD < 3.6 V,

VOS0, CLOAD = 15 pF

90(4)

MHz

1.71 V < VDD < 3.6 V,

VOS0, CLOAD = 20 pF

87(4)

2.7 V < VDD < 3.6 V,

VOS0, CLOAD = 20 pF

110

tw(CKH)

OCTOSPI clock high and

low time, even division

PRESCALER[7:0] = n

= 0,1,3,5

t(CK)/2

t(CK)/2+1

tw(CKL)

t(CK)/2–1

t(CK)/2

tw(CKH)

OCTOSPI clock high and

low time, odd division

PRESCALER[7:0] = n

= 2,4,6,8

(n/2)*t(CK)/

(n+1)

(n/2)*t(CK)/

(n+1)+1

tw(CKL)

(n/2+1)*t(CK)/(

n+1) – 1

(n/2+1)*

t(CK)/(n+1)

tsr(IN)

tsf(IN)(5)

Data input setup time

3.0

thr(IN)

thf(IN)(5)

Data input hold time

1.50

tvr(OUT)

tvf(OUT)

Data output valid time

DHQC = 0

7(6)

DHQC = 1,

Prescaler = 1,2 ...

tpclk/4+

tpclk/4+1.25

(6)

thr(OUT)

thf(OUT)

Data output hold time

DHQC = 0

4.5

DHQC = 1,

Prescaler = 1,2 ...

tpclk/4

1. All values apply to Octal and Quad-SPI mode.

2. Guaranteed by characterization results.

3. DHQC must be set to reach the mentioned frequency.

4. Using PC2 or PC3 I/O in the data bus decreases the frequency to 47 MHz.

5. Delay block bypassed.

6. Using PC2 or PC3 I/O in the data bus adds 4 ns to this timing value.

MSv36879V1

Data output

Clock

Data input

t(CK)

tw(CKH)

tw(CKL)

tr(CK)

tf(CK)

tsf(IN) thf(IN)

tvf(OUT)

thr(OUT)

tvr(OUT)

thf(OUT)

tsr(IN) thr(IN)

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