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STM32H723VG Datasheet(PDF) 154 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 154 Page - STMicroelectronics |
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154 / 227 page ![]() Electrical characteristics STM32H723xE/G 154/227 DS13313 Rev 2 Figure 34. OCTOSPI Hyperbus clock timing diagram Figure 35. OCTOSPI Hyperbus read timing diagram 2. Maximum frequency values are given for a RWDS to DQ skew of maximum +/-1.0 ns. 3. Activating DHQC is mandatory to reach this frequency 4. Using PC2 or PC3 I/O on data bus decreases the frequency to 47 MHz. 5. Using PC2 or PC3 I/O on the data bus adds 4 ns to this timing value. MSv47732V2 CK tr(CK) tw(CKH) tw(CKL) t(CK) tf(CK) VOD(CK) MSv47733V2 CS# tACC= Initial Access Latency Count Command-Address 47:40 39:32 31:24 23:16 15:8 7:0 Dn A Dn B Dn+1 A Dn+1 B Host drives DQ[7:0] and Memory drives RWDS CK RWDS DQ[7:0] Memory drives DQ[7:0] and RWDS tw(CS) tv(RWDS) tv(CK) tv(DS) tv(DQ) th(CK) th(DS) tv(OUT) th(OUT) th(DQ) ts(DQ) |
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