PIMXRT516SCVM5A datasheet(14/124 Pages) NXP

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i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

Modules list

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

GPIO6

GPIO7

GPIO8

GPIO9

GPIO10

GPIO11

GPIO12

GPIO13

General Purpose I/O

Modules

System Control

Peripherals

Used for general purpose input/output to external ICs.

Each GPIO module supports up to 32 bits of I/O.

Note: GPIO13 register access takes a long time (about

s due to clocked by 32 KHz clock source). During the

period of registers access, the LPSR domain bus would

be on hold.

GPT1

GPT2

GPT3

GPT4

GPT5

GPT6

General Purpose Timer

Timer Peripherals

Each GPT is a 32-bit “free-running” or “set and forget”

mode timer with programmable prescaler and compare

and capture register. A timer counter value can be

captured using an external event and can be configured

to trigger a capture event on either the leading or trailing

edges of an input pulse. When the timer is configured to

operate in “set and forget” mode, it is capable of

providing precise interrupts at regular intervals with

minimal processor intervention. The counter has output

compare logic to provide the status and interrupt at

comparison. This timer can be configured to run either

on an external clock or on an internal clock.

GPU2D

Graphics Processing

Multimedia

Peripherals

The vector graphics processing supports following

features:

• Real-time hardware curve tessellation of lines,

quadratic, and cubic Bezier curves

• 16x line anti-aliasing

• OpenVG 1.1 support

• Vector drawing

IOMUXC

IOMUX Control

Mux control

This module enables flexible I/O multiplexing. Each IO

pad has a default as well as several alternate functions.

The alternate functions are software configurable.

JTAGC

JTAG Controller

System Control

Peripherals

The JTAG interface complies with JTAG TAP standards

to internal logic. The i.MX RT1160 processors use JTAG

port for production, testing, and system debugging. In

addition, the JTAG provides BSR (Boundary Scan

1149.1 and IEEE 1149.6 standards.

The JTAG port must be accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX RT1160 JTAG

incorporates two security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

Table 3. i.MX RT1160 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT516SCVM5A Datasheet(PDF) 14 Page - NXP Semiconductors

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