PIMXRT516SCVM5A datasheet(17/124 Pages) NXP

17 / 124 page

Modules list

i.MX RT1160 Crossover Processors Data Sheet for Industrial Products, Rev. 0, 04/2021

NXP Semiconductors

PIT1

PIT2

Periodical Interrupt Timer

Timer Peripherals

The PIT features 32-bit counter timer, programmable

count modules, clock division features, interrupt

generation, and a slave mode to synchronize count

enable for multiple PITs.

PXP

Pixel Processing Pipeline

Multimedia

Peripherals

A high-performance pixel processor capable of 1

pixel/clock performance for combined operations, such

as color-space conversion, alpha blending, and rotation.

The PXP is enhanced

with features specifically for gray scale applications. In

addition, the PXP supports traditional pixel/frame

processing paths for still-image and video processing

applications.

Quadrature DEC1

Quadrature DEC2

Quadrature DEC3

Quadrature DEC4

Quadrature Decoder

Timer Peripherals

The enhanced quadrature decoder module provides

interfacing capability to position/speed sensors. There

are five input signals: PHASEA, PHASEB, INDEX,

TRIGGER, and HOME. This module is used to decode

shaft position, revolution count, and speed.

QuadTimer1

QuadTimer2

QuadTimer3

QuadTimer4

QuadTimer

Timer Peripherals

The quad-timer provides four time channels with a

variety of controls affecting both individual and

multi-channel features.Specific features include

up/down count, cascading of counters, programmable

module, count once/repeated, counter preload,

compare registers with preload, shared use of input

signals, prescaler controls, independent

capture/compare, fault input control, programmable

input filters, and multi-channel synchronization.

RDC

Resource Domain

Controller

Security

The RDC provides robust support for the isolation of

processing domain to prevent one core from accessing

another’s peripherals, to control access rights to

common memory and provide hardware enforcement of

semaphore based locking of shared peripherals.

For single system use case, RDC can be disabled and

AIPS-TZ/DEXSC can be bypassed. For dual system

case, RDC can be configured and locked each core

starts their own image.

ROMCP

ROM Controller with

Patch

Memories and

Memory Controllers

The ROMCP acts as an interface between the Arm

advanced high-performance bus and the ROM. The

on-chip ROM is only used by the Cortex-M7 core during

boot up. Size of the ROM is 256 KB.

RTC OSC

Real Time Clock

Oscillator

Clock Sources and

Control

The RTC OSC provides the clock source for the

Real-Time Clock module. The RTC OSC module, in

conjunction with an external crystal, generates a 32.768

kHz reference clock for the RTC.

SAI1

SAI2

SAI3

SAI4

Synchronous Audio

Interface

Multimedia

Peripherals

The SAI module provides a synchronous audio interface

(SAI) that supports full duplex serial interfaces with

frame synchronization, such as I2S, AC97, TDM, and

codec/DSP interfaces.

Table 3. i.MX RT1160 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

PIMXRT516SCVM5A Datasheet(PDF) 17 Page - NXP Semiconductors

PIMXRT516SCVM5A Datasheet(HTML) 17 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL